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Probabilistic modelling of performance parameters of Carbon Nanotube transistors Department of Electrical and Computer Engineering By Yaman Sangar Amitesh Narayan Snehal Mhatre

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology - Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 1

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 2

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MOTIVATION: Why CNTFET? 04/29/ Dennard Scaling might not last long Increased performance by better algorithms? More parallelism? Alternatives to CMOS - FinFETs, Ge-nanowire FET, Si- nanowire FET, wrap-around gate MOS, graphene ribbon FET What about an inherently faster and less power consuming device? Yay CNTFET – faster with low power

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 4

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5 Carbon Nanotubes 04/29/2014 CNT is a tubular form of carbon with diameter as small as 1nm CNT is configurationally equivalent to a 2-D graphene sheet rolled into a tube.

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6 Types of CNTs 04/29/2014 Single Walled CNT (SWNT) Double Walled CNT (DWNT) Multiple Walled CNT (MWNT) Depending on Chiral angle: Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)

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7 Properties of CNTs 04/29/2014 Strong and very flexible molecular material Electrical conductivity is 6 times that of copper High current carrying capacity Thermal conductivity is 15 times more than copper Toxicity?

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04/29/ CNTFET How CNTs conduct? Gate used to electrostatically induce carriers into tube Ballistic Transport

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 9

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CircuitFETDelay (In Picoseconds) Power (In uWatts) InverterCMOS CNT Input NandCMOS CNT Input NorCMOS CNT Simulation based Comparison between CMOS and CNT technology 04/29/

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04/29/ Better delay CircuitFETDelay (In Picoseconds) Power (In uWatts) InverterCMOS CNT Input NandCMOS CNT Input NorCMOS CNT Simulation based Comparison between CMOS and CNT technology

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04/29/ Better delay At lower power! CircuitFETDelay (In Picoseconds) Power (In uWatts) InverterCMOS CNT Input NandCMOS CNT Input NorCMOS CNT Simulation based Comparison between CMOS and CNT technology

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/

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Major CNT specific variations CNT density variation Metallic CNT induced count variation CNT diameter variation CNT misalignment CNT doping variation Challenges with CNT technology 04/29/ Unavoidable process variations Performance parameters affected

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CNT density variationCNT diameter variation Current variation Threshold voltage variation 04/29/

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CNT Misalignment CNT doping variation Changes effective CNT length Short between CNTs Incorrect logic functionality Reduction in drive current May not lead to unipolar behavior 04/29/

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Metallic CNT induced count variation m-CNT s-CNT Excessive leakage current Increases power consumption Changes gate delay Inferior noise performance Defective functionality s-CNT m-CNT Vgs Current 04/29/

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18 Removal of m-CNTFETs VMR Technique : A special layout called VMR structure consisting of inter-digitated electrodes at minimum metal pitch is fabricated. M-CNT electrical breakdown performed by applying high voltage all at once using VMR. M-CNTs are burnt out and unwanted sections of VMR are later removed. Using Thermal and Fluidic Process: Preferential thermal desorption of the alkyls from the semiconducting nanotubes and further dissolution of m-CNTs in chloroform. Chemical Etching: Diameter dependent etching technique which removes all m-CNTs below a cutoff diameter. 04/29/2014

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/

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Probabilistic model of CNT count variation due to m-CNTs p s = probability of s-CNT p m = probability of m-CNT p s = 1 - p m N gs = number of grown s-CNTs N gm = number of grown m-CNTs N= total number of CNTs Probability of grown CNT count 04/29/

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Conditional probability after removal techniques N s = number of surviving s-CNTs N m = number of surving m-CNTs p rs = conditional probability that a CNT is removed given that it is s-CNT p rm = conditional probability that a CNT is removed given that it is m-CNT q rs = 1 - p rs q rm = 1 -p rm 04/29/

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/

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Effect of CNT count variation on I ON / I OFF tuning ratio I ON / I OFF is indicator of transistor leakage Improper I ON / I OFF slow output transition or low output swing Target value of I ON / I OFF = /29/

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Current of a single CNT I CNT = p s I s + p m I m µ(I CNT ) = p s µ( I s )+ p m µ(I m ) I CNT = drive current of single CNT (type unknown) I s = drive current of single s-CNT I m = drive current of single m-CNT p s = probability of s-CNT p m = probability of m-CNT 04/29/

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I ON / I OFF ratio of CNTFET 04/29/

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µ (N s ) = p s (1 - p rs ) N µ (N m ) = p m (1 - p rm ) N I ON / I OFF ratio of CNTFET 04/29/

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Effect of various processing parameters on the ratio µ(I ON ) / µ(I OFF ) µ(I ON ) / µ(I OFF ) is more sensitive to p rm µ(I ON ) / µ(I OFF ) = 10 4 for p rm > 1 – = % for p m = 33.33% 04/29/ p rm

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/

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29 04/29/2014 Effect of CNT count variation on Gate delay

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30 04/29/2014

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31 04/29/2014 N = 10 N = 20 N = 30 N = 40 N = 50

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32 04/29/2014 N

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/

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34 Noise Margin of CNTFET 04/29/2014

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35 V IL and V IH 04/29/2014 nFET pFET

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04/29/ For CNTFET, For CMOS, V IL and V IH NM L = V IL - 0 NM H = V DD – V IH

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Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: I ON / I OFF tuning ratio Gate delay Noise Margin Conclusion 04/29/

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38 CONCLUSION Modeled count variations and hence device current as a probabilistic function Studied the affect of these faults on tuning ratio and gate delay Inferred some design guidelines that could be used to judge the correctness of a process Mathematically derived noise margin based on current equations – better noise margin than a CMOS 04/29/2014

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