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Commande dactionneurs à laide dun microprocesseur 1 Prise en main du DSP Christian Koechli.

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Presentation on theme: "Commande dactionneurs à laide dun microprocesseur 1 Prise en main du DSP Christian Koechli."— Presentation transcript:

1 Commande dactionneurs à laide dun microprocesseur 1 Prise en main du DSP Christian Koechli

2 Composants de lélectronique de commande CPU: DSP ou contrôleur Driver MesureCapteurs Alim puissance Signaux logiques Signaux de commande Signaux de mesure Alim. de la « logique »

3 Texas Instruments TMS320F28069 Processeur 32 bits Architecture Harvard F=90MHz (80 protos) FPU / CLA 256 kB flash 100 kB RAM 1 AD (16 canaux 12 bits 3MSps) SPI/I2C/CAN/USB 2 RS232 54 GPIO 3 CAPTURE +4 HRCap+ 2eQep 8 ePWM

4 F28069 Block Diagram

5 Memory Map

6 Gestion de la mémoire

7 Watchdog Timer

8 General Purpose IO

9 GPIO Multiplexing

10

11

12 Exemple de programmation extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; extern volatile struct GPIO_DATA_REGS GpioDataRegs; struct GPIO_CTRL_REGS { union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) Uint32 rsvd1; // reserved union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) Uint16 rsvd2[24];// reserved union AIO_REG AIOMUX1; // Analog IO Mux 1 Register (AIO0 to 15) Uint32 rsvd3; // reserved union AIODAT_REG AIODIR; // Analog IO Direction Register (AIO0 to 15) Uint16 rsvd4[5]; // reserved };

13 Exemple de programmation struct GPIO_DATA_REGS { union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31) union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31) union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31) union GPBPUD_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63) union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63) union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32to 63) Uint16 rsvd1[8]; // reserved union AIODAT_REG AIODAT; // Analog IO Data Register (AIO0-15) Uint16 rsvd2; union AIODAT_REG AIOSET; // Analog IO Data Set Register (AIO0-15) Uint16 rsvd3; union AIODAT_REG AIOCLEAR; // Analog IO Data Clear Register (AIO0-15) Uint16 rsvd4; union AIODAT_REG AIOTOGGLE; // Analog IO Data Toggle Register (AIO0-15) Uint16 rsvd5; }; Au reset toutes les pates sont configurées comme IO/input. Pour configurer la patte EPWM1A comme périphérique EPWM : EALLOW; GpioCtrlRegs.GPAMUX1.bit.GPIO0=1 ; EDIS;

14 Interrupts

15 A valid signal on a specific interrupt line causes the latch to display a 1 in the appropriate bit A valid signal on a specific interrupt line causes the latch to display a 1 in the appropriate bit Maskable Interrupt Processing Conceptual Core Overview1 0 1 (IFR) LatchINT1 INT2 INT14CoreInterruptC28xCore (INTM) Global Switch (IER) Switch If the individual and global switches are turned on the interrupt reaches the core If the individual and global switches are turned on the interrupt reaches the core

16 Interrupt Flag Register (IFR) RTOSINTDLOGINTINT14INT13INT12INT11INT10INT9 8 9 1011121314 15 INT8INT7INT6INT5INT4INT3INT2INT1 0 1234567 Pending :IFR Bit = 1 Absent :IFR Bit = 0 Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR If interrupt occurs when writing IFR, interrupt has priority If interrupt occurs when writing IFR, interrupt has priority IFR(bit) cleared when interrupt is acknowledged by CPU IFR(bit) cleared when interrupt is acknowledged by CPU Register cleared on reset Register cleared on reset /*** Manual setting/clearing IFR ***/ extern cregister volatile unsigned int IFR; IFR |= 0x0008;//set INT4 in IFR IFR |= 0x0008;//set INT4 in IFR IFR &= 0xFFF7;//clear INT4 in IFR IFR &= 0xFFF7;//clear INT4 in IFR

17 Interrupt Enable Register (IER) RTOSINTDLOGINTINT14INT13INT12INT11INT10INT9 8 9 1011121314 15 INT8INT7INT6INT5INT4INT3INT2INT1 0 1234567 Enable: Set IER Bit = 1 Disable: Clear IER Bit = 0 Compiler generates atomic instructions (non-interruptible) for setting/clearing IER Compiler generates atomic instructions (non-interruptible) for setting/clearing IER Register cleared on reset Register cleared on reset /*** Interrupt Enable Register ***/ extern cregister volatile unsigned int IER; IER |= 0x0008;//enable INT4 in IER IER |= 0x0008;//enable INT4 in IER IER &= 0xFFF7;//disable INT4 in IER IER &= 0xFFF7;//disable INT4 in IER

18 Interrupt Global Mask Bit INTM used to globally enable/disable interrupts: –Enable:INTM = 0 –Disable:INTM = 1 (reset value) INTM modified from assembly code only: INTM ST1 Bit 0 Bit 0 /*** Global Interrupts ***/ asm( CLRC INTM); //enable global interrupts asm( CLRC INTM); //enable global interrupts asm( SETC INTM); //disable global interrupts asm( SETC INTM); //disable global interrupts

19 F28069 PIE Interrupt Assignment Table

20

21 Déroulement dun appel dinterruption


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