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Course: Low power design of electronic circuits Student: Ahmed Faraz

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Index Objective Basic idea Basic gating circuit and linear feedback shift register Design platform Final circuit Results Conclusion

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Objective To reduce the power of 16-bit linear feedback shift register(LFSR) using gated clock. To measure the Average, Maximum and Minimum Power in Traditional 16-bit LFSR. To measure the Average, Maximum and Minimum Power in 16-bit gated clock LFSR.

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What is Linear feedback shift register? A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. For 16 bit LFSR-feedback polynomial is x 16 + x 14 + x 13 + x 11 + 1

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Basic idea Since, in LFSR, the clock-path of all flip-flop toggles at every clock cycle, they consume a significant amount of power. To activate flip flop only when the input signal is different from the actual output value.

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Design Platform Average Power Minimum PowerMaximum Power Verilog gatenetlist Design Architect (ELDO) VHDL Code (Designed, compiled and simulated in MODELSIM) Leonardo Spectrum

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16 bit linear feedback shift register

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16 bit Linear feedback shift register with gated clock

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Results Without clock gatingWith clock gating Maximum power37.939 mW30.144 mW Minimum power45.6137 nW62.4403 nW Average power5.6966 mW4.913 mW

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Comparison

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Conclusion Average power consumed has been decreased, whereas Minimum power has been increased which may be due to the initial power consumption at the time of initializing the LFSR.

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References Dr. Vishwani Agrawal: Slides Spring 2009.Low Power Design of Electronic Circuits. Utilizing clock-gating efficiency to reduce power By Mitch Dale: EE TIMES-INDIA JANUARY 2008 Gated-Clock Design of Linear-Feedback Shift Registers By Walter Aloisi and Rosario Mita: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-2: EXPRESS BRIEFS, VOL.55,NO.6,JUNE 2008.

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