# CSE245: Computer-Aided Circuit Simulation and Verification Lecture Note 4 Model Order Reduction (2) Spring 2010 Prof. Chung-Kuan Cheng 1.

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CSE245: Computer-Aided Circuit Simulation and Verification Lecture Note 4 Model Order Reduction (2) Spring 2010 Prof. Chung-Kuan Cheng 1

Model Order Reduction: Overview Explicit Moment Matching –AWE, Pade Approximation Implicit Moment Matching (Projection Framework) –Krylov Subspace Methods PRIMA, SPRIM Gaussian Elimination –TICER, Y-Delta Transformation 2

Conventional Design Flow Function Sepc RTL Logic Synth. Gate-level Net. Floorplanning Place & Route Layout Front-end Back-end Beh. Simul Stat. Wire Model Gate-Lev. Sim Para. Extraction Parasitics resistance, capacitance and inductance cause noise, energy consumption and power distribution problem 3

Parasitic Extraction R,L,C Extraction Model Order Reduction 4

Moment Matching Projection method Key ideal of Model Order reduction: Moments Matching and Projection Step1: identify internal state function and variables. Step2: Compose moments matching. (Pade, Taylor expression). Step3: Project matrix with matching moments. (Block Arnoldi (PRIMA) or block Lanczos (PVL)) Step4: Get the reduced state function. 5

Explicit V.S. Implicit Moment Matching Explicit moment matching methods –Numerically ill-conditioned Implicit moment matching methods –construct reduced order models through projection, or congruence transformation. –Krylov subspaces vectors instead of moments are used. 6

Congruence Transformation Definition: Property: Congruence transformation preserves semidefiniteness of the matrix 7

Krylov Subspace Given an n x n matrix A and a n x 1 vector r the Krylov subspace is defined as Given an n x q matrix V q whose column vectors are v 1, v 2, …, v q. The span of V q is defined as 8

PRIMA Passive Reduced-order Interconnect Macromodeling Algorithm. –Krylov subspace based projection method –Reduced model generated by PRIMA is passive and stable. where PRIMA (system of size n) (system of size q, q< { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/4/1473344/slides/slide_9.jpg", "name": "PRIMA Passive Reduced-order Interconnect Macromodeling Algorithm.", "description": "–Krylov subspace based projection method –Reduced model generated by PRIMA is passive and stable. where PRIMA (system of size n) (system of size q, q<

PRIMA step 1. Circuit Formulation step 2. Find the projection matrix V q –Arnoldi Process to generate V q 10

PRIMA: Arnoldi 11

PRIMA step 3. Congruence Transformation 12

PRIMA: Properties Preserves passivity, and hence stability Matches moments up to order q (proof in next slide) Original matrices A and C are structured. But and do not preserve this structure in general 13

PRIMA: Moment Matching Proof Used lemma 1 14

PRIMA: Lemma Proof 15

SPRIM Structure-Preserving Reduced-Order Interconnect Macromodeling –Similar to PRIMA except that the projection matrix V q is different –Preserves twice as many moments as PRIMA –Preserves structure –Preserves passivity, stability and reciprocity –Matching the same number of moment as PRIMA, but preserve the structure which can reduced numerical calculation. 16

SPRIM Suppose V q is generated by Arnoldi process as in PRIMA. Partition V q accordingly Recall Construct New Projection Matrix 17

SPRIM Congruence Transformation Now structure is preserved Transfer function for the reduced order model 18

Traditional Y- Transformation Conductance in series Conductance in star-structure n1n1 n2n2 n1n1 n2n2 n1n1 n1n1 n2n2 n3n3 n2n2 n3n3 n0n0 n0n0 19

TICER (TIme Constant Equilibration Reduction) 1) Calculate time constant for each node 2) Eliminate quick nodes and slow nodes –Quick node: Eliminate if –Slow node: Eliminate if 3) Insert new R s/C s between former neighbors of N –If nodes j and k had been connected to N through g jN and g kN, add a conductance of value g jN g kN /G N between j and k –If nodes j and k had been connected to N through c jN and g kN, add a capacitor of value c jN g kN /G N between j and k 20

TICER: Issues Fill-in –The order that nodes are eliminated matters Minimum Degree Ordering can be implemented to reduce fill-in –May need to limit number of incident resistors to control fill-in Error control leads to low reduction ratio Accuracy –Matches 0 th moment at every node in the reduced circuit. –Only Correct DC op point guaranteed 21

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