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Copyright 1995-1999 SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Modeling for Embedded Digital.

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Presentation on theme: "Copyright 1995-1999 SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Modeling for Embedded Digital."— Presentation transcript:

1 Copyright SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Modeling for Embedded Digital Systems Design RASSP Education & Facilitation Program Module 57 Version 3.00 Copyright SCRA All rights reserved. This information is copyrighted by the SCRA, through its Advanced Technology Institute (ATI), and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the ATI is prohibited. Certain parts of this work belong to other copyright holders and are used with their permission. All information contained, may be duplicated for non-commercial educational use only provided this copyright notice and the copyright acknowledgements herein are included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. The United States Government holds Unlimited Rights in all data contained herein under Contract F C Such data may be liberally reproduced and disseminated by the Government, in whole or in part, without restriction except as follows: Certain parts of this work to other copyright holders and are used with their permission; This information contained herein may be duplicated only for non-commercial educational use. Any vehicle, in which part or all of this data is incorporated into, shall carry this notice.

2 Copyright SCRA 2 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Rapid Prototyping Design Process SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN Cost Modeling for Embedded Digital Systems Design

3 Copyright SCRA 3 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP l Establish the importance of system engineering constraints on embedded system design. l Survey the methods of cost estimation and modeling for hardware and software design, implementation, and test. l Introduce a cost-modeling based design methodology for embedded systems using cost estimators and performance modeling. l Understand the benefits of cost modeling through application to an embedded system case study. Goals

4 Copyright SCRA 4 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design m Limitations of Typical Design Process m Effect of HW Resource Constraints HW/SW Prototyping Costs/Schedule m Effect of System Development Time on Expected Revenue m Cost Modeling in the Early Stages of Design l Software Cost Estimation Process m Software Life Cycle Models m Basic Steps in the Software Cost Estimating Process

5 Copyright SCRA 5 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline (Cont.) l Parametric Software Cost Models m COCOMO m REVIC m COCOMO 2.0 l Parametric Hardware Cost Models m Full Custom m Gate Array m FPGA

6 Copyright SCRA 6 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline (Cont.) l Applications of Cost Modeling in the RASSP Design Process m Classifications of System-Level Design & Test Methodologies m Example Automated Cost-Driven Architecture Selection/Sizing Model m Case Study: Synthetic Aperture Radar (SAR) Image Processor m Results: Detailed Cost Analysis for SAR Benchmark l Summary and Major Issues

7 Copyright SCRA 7 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design l Software Cost Estimation Process l Parametric Software Cost Models l Parametric Hardware Cost Models l Applications of Cost Modeling to the RASSP Design Process l Summary and Major Issues

8 Copyright SCRA 8 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Motivation for Cost Modeling in the Design Process l Design Challenge: m Designers of high-end embedded systems or large volume commercial consumer products are faced with the formidable challenge of rapidly prototyping cost- effective implementations which meet: q Stringent performance specifications q Formidable functional and timing requirements q Tight physical constraints l System life cycle cost and time-to-market cost are key factors which determine successful products in the competitive electronics marketplace m These key factors should have a dominant influence on the design of embedded microelectronic systems

9 Copyright SCRA 9 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Complexity of the Design Space for Embedded Systems l A combinatorially significant number of alternatives exist in the implementation of high performance embedded systems Key Architectural Attributes l Computational elements l Communication elements l Topologies l Software (Application, Control & Diagnostics) l Analog Interfaces l Mechanical Interfaces Key Architectural Attributes l Computational elements l Communication elements l Topologies l Software (Application, Control & Diagnostics) l Analog Interfaces l Mechanical Interfaces Customer Requirements l Functionality and Performance l Deployment Schedule l Interfaces and Packaging l Size, Volume, and Weight l Power l Environment l Cost l Software and Hardware Modularity l Security l Scalability l Reliability and Maintainability Customer Requirements l Functionality and Performance l Deployment Schedule l Interfaces and Packaging l Size, Volume, and Weight l Power l Environment l Cost l Software and Hardware Modularity l Security l Scalability l Reliability and Maintainability

10 Copyright SCRA 1010 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Typical Prototyping Process Flow Limitations êlong prototyping times êhigh cost of design êin-cycle silicon fabrication and test êadhoc techniques used to make architectural and packaging trade- offs êlack of systematic reuse êlack of coupling between HW and SW design efforts System Requirements Definition System Architecture Definition Hardware Design Software Design Inter- face Design Hardware Manufacture & Test Software Code & Test Hardware/Software Integration & Test Field Test Deliverables Documentation Production & Deployment months months months [MAD96] © IEEE 1996

11 Copyright SCRA1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP HW/SW Cost Trends Software Maintenance Development Hardware Year Percent of total costs

12 Copyright SCRA 1212 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Example for Modeling Software Development Cost/Time Software Development Time where l C - constant used to capture multiplicative effects on time with projects of increasing effort (DEFAULT = 6.2) l D - scale factor which accounts for the relative economies or diseconomies of scale encountered for projects of different required efforts (DEFAULT = 0.32) l PSCED - the percent compression/expansion to the nominal deployment schedule l F E, F M, F SCED -execution time, main storage, and schedule constraint effort multipliers Software Development Time where l C - constant used to capture multiplicative effects on time with projects of increasing effort (DEFAULT = 6.2) l D - scale factor which accounts for the relative economies or diseconomies of scale encountered for projects of different required efforts (DEFAULT = 0.32) l PSCED - the percent compression/expansion to the nominal deployment schedule l F E, F M, F SCED -execution time, main storage, and schedule constraint effort multipliers Software Development Effort where l KSLOC - thousands of source lines of code l A - constant used to capture the multiplicative effects on effort with projects of increasing size (DEFAULT = 4.44) l B - scale factor which accounts for the relative economies or diseconomies of scale encountered for software projects of different sizes (DEFAULT = 1.2 -> diseconomy) l F i s - cost drivers which model the effect of personnel, computer, product, and project attributes on software cost Software Development Effort where l KSLOC - thousands of source lines of code l A - constant used to capture the multiplicative effects on effort with projects of increasing size (DEFAULT = 4.44) l B - scale factor which accounts for the relative economies or diseconomies of scale encountered for software projects of different sizes (DEFAULT = 1.2 -> diseconomy) l F i s - cost drivers which model the effect of personnel, computer, product, and project attributes on software cost Embedded Mode REVIC (REVised Intermediate COCOMO) Model l Predicts software development life-cycle costs l Costs including requirements analysis through completion of software acceptance testing l Maintenance life-cycle costs for fifteen years

13 Copyright SCRA 1313 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Execution Time, F E, and Main Storage Constraint, F M, Effort Multipliers Effort Multiplier Value Hardware Resource Utilization(%) Execution-Time Constraint Effort Multiplier Main Storage Constraint Effort Multiplier

14 Copyright SCRA 1414 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Impact of Schedule Compression/Extension Effort Multiplier Value Relative Schedule Length, PSCED (% of nominal schedule) Schedule Constraint Effort Multiplier

15 Copyright SCRA 1515 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Effect of HW Resource Constraints on HW/SW System Prototyping Costs 100 Relative SW Development Cost Utilization of available speed and memory - Infeasible region due to form constraints Software Dev. Cost Hardware Dev. Cost HW/SW System Dev. Cost

16 Copyright SCRA 1616 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Design Trade-off Example: SAR Processor with COTS Multiprocessor Cards 1 MINIMUM HARDWARE COST - LOWEST PRODUCTION COST - MINIMUM SIZE, WEIGHT, & POWER - NOMINAL MEMORY & COMPUTATION MARGINS 2 REDUCED DEVELOPMENT COST & TIME - SAME NUMBER OF CARDS AND LIFE CYCLE COST AS - RAM ADDED TO IMPROVE MEMORY MARGIN, ALLOW USE OF ADVANCED SOFTWARE DEVELOPMENT TOOLS AND METHODOLOGY 3 MINIMUM DEVELOPMENT COST & TIME - PROCESSORS ADDED TO - IMPROVED COMPUTATION MARGIN FURTHER EASES SOFTWARE DEVELOPMENT COST ($M) DEVELOPMENT SCHEDULE (YEARS) HW SW TOTAL HW SW TOTAL SW TOTAL HW 3.8X 1.5X [AND95]

17 Copyright SCRA 1717 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Potential Effect of Packaging on Prototyping Costs Cost (person hours, dollars) Utilization of available speed and memory 0.x0.y1.00.z Software Cost Hardware cost (small quantity production) A B C D E F - Single chip packaging infeasible due to form constraints - MCM and single chip packaging infeasible due to form constraints Combined HW/SW System Cost

18 Copyright SCRA 1818 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Effect of HW Resource Constraints on Schedule 100 Relative SW Development Cost Utilization of available speed and memory - Infeasible region due to form constraints Software Development Time

19 Copyright SCRA 1919 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Effect of Schedule Delays on Time-to-Market Cost l Time-to-market costs can often outweigh design, prototyping, and production costs l Reasons: m When competitors beat you to market with a comparable product, they gain considerable market share and brand name recognition m An earlier market entry has more opportunity to improve yield, thereby improving profits m Design and prototyping costs are an up front investment that must produce a return as soon as possible q The longer investors must wait for a return, the higher the return must be

20 Copyright SCRA 2020 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Time-to-Market Cost (Cont.) l Surveys have shown that being six months late to market resulted in an average of 33% profit loss for that product m A 9% production cost overrun resulted in a 21% loss m A 50% design development cost overrun resulted in only a 3% profit loss l Engineering managers stated that they would rather have a 100% overrun in design and prototyping costs than be three months late to market with a product

21 Copyright SCRA 2121 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Time-to-Market Cost Models l Simple quantitative time-to-market models can be used to estimate the cost of delivering a product to market late l Examples: m Simplified triangular time-to-market model m Growth-Stagnation-Decline (GSD) time-to-market model

22 Copyright SCRA2 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Triangular Time-to-Market Cost Model Revenues ($) Maximum Available Revenue Maximum Revenue from Delayed Entry Market RiseMarket Fall Time-to-market System Concept Production & Deployment D WW Product Life = 2W Time (months) Revenue Loss Equation

23 Copyright SCRA 2323 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP GSD Time-to-Market Model Revenues ($) System Concept Time (months) Time-to-market Production & Deployment D W1W1 SW2W2 (Growth)(Stagnation)(Decline) Revenue Loss Equation Maximum Available Revenue Maximum Revenue from Delayed Entry Market RiseMarket Fall

24 Copyright SCRA 2424 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Economic Cost-Driven System-Level Design l To effectively address these system-level design challenges, a unified approach that considers the cost attributes of software options and hardware options is required. l Solution: Economic Cost-Driven System-Level Design m This concept attempts to converge the hardware and software design efforts into a combined methodology that improves cost, cycle time, and quality, which enhancing the exploration of the HW/SW design space. m Parametric cost and development time estimation models are used to drive the design process m A cost estimation-driven architecture design engine is seamlessly integrated within a hardware-less, library-based cosimulation and coverification environment for rapid prototyping

25 Copyright SCRA 2525 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Overall Library-Based System Design Methodology Application Behavior Test & Stimuli Performance Constraints Form Factor Constraints Schedule Constraints HW/SW Partitioning Architecture/ Packaging Selection Task Assignment/ Scheduling Performance Modeling Compare Conceptual Prototyping SW Reuse Libraries Virtual Prototyping Compare Field Prototype FAB Manufact. Assembly Software Off cycle updates Metrics Collection Interoperable Tool Suites/Enterprise Int. VHDL HW Model Reuse Libraries HW Modelers Emulation Tools Off cycle updates SE/EE Interfaces

26 Copyright SCRA 2626 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Committed Over the Product Life Cycle 20% 40% 60% 80% 100% concept design engineering testing process planning production Cost Committed Cost Incurred time

27 Copyright SCRA 2727 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost-Driven Front-End Design Process Form Factor Constraints Performance Requirements Memory/ Communication Requirements APPLICATION REQUIREMENTS Functional Requirements Software Reuse Library Performance Benchmarks Schedule Constraints Manpower Constraints COTS Processor-Memory Board Prices COTS Processor-Memory Board Form Factor Ratings Labor Rates Software Size SW Development Cost Driver Attribute Ratings Expected Product Revenue Production Volume Expected Product Lifetime SYSTEM-LEVEL COST PARAMETERS Estimated Communication Overhead Cost-Driven Architecture Selection Task Assignment Task Scheduling Performance Modeling HW/SW Architectural Candidates Executable Requirement

28 Copyright SCRA 2828 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design l Software Cost Estimation Process l Parametric Software Cost Models l Parametric Hardware Cost Models l Applications of Cost Modeling to the RASSP Design Process l Summary and Major Issues

29 Copyright SCRA 2929 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Life Cycle Models l Software life cycle models identify various phases and associated activities required to develop and maintain software l Some common life cycle models include: m Waterfall model m Spiral development model m Reusable software model l Models form a baseline from which to begin the software estimation process

30 Copyright SCRA 3030 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Waterfall Model System Feasibility Validation Software plans and requirements Validation Product DesignVerification Detailed DesignVerification CodeUnit Test Integration Product Verification Implementation System Test Operations and maintenance Revalidation [BOEHM88] © IEEE 1988

31 Copyright SCRA 3131 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Spiral Model Review Commitment partition Determine objectives, alternatives, constraints Evaluate alternatives, identify, resolve risks Develop, verify next-level product [BOEHM88] Plan next phases Progress through steps Cumulative Cost Risk analy- sis Pro- totype1 Concept of operation Requirements plan life cycle plan Risk analysis Prototype 2 Risk analysis Prototype 3 Operational prototype Simulations, models, benchmarks Software requirements Requirements validation Development plan Software product design Design validation & verification Integration and test plan Detailed Design Code Unit Test Integration & Test Acceptance Test Implemen- tation © IEEE 1988

32 Copyright SCRA 3232 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Legacy and Reuse Software Life Cycle Requirements Component specifications Architecture Design Application/reuse software Transformed software Legacy software [AHRENS95] © IEEE 1995

33 Copyright SCRA3 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Basic Software Cost Estimation Process l The software cost estimation activity is a miniproject l Basic Steps m Define project objectives and requirements m Plan the software estimation activities q Develop detailed work breakdown structure (WBS) m Estimate software size m Define and weigh potential software estimation risks m Use several independent cost estimation methodologies

34 Copyright SCRA 3434 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Establish Objectives l Guidelines for establishing the objectives of a cost estimation activity 1. Key the estimating objectives to the needs for decision making information 2. Balance the estimating accuracy objectives for the various system components of the cost estimates 3. Re-examine estimating objectives as the process proceeds, and modify them where appropriate

35 Copyright SCRA 3535 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Pin Down Software Requirements l The best way to determine to what extent a software specification is costable is to determine to what extent it is testable. l A specification is testable to the extent that one can define a clear pass/fail test for determining whether or not the developed software will satisfy the specification. l In order to be testable, specifications must be specific, unambiguous, and quantitative wherever possible.

36 Copyright SCRA 3636 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Develop a Software Work Breakdown Structure (WBS) l The WBS helps to establish a hierarchical view and organization of the project l The WBS should depict only: m major software functions q computer software configuration items (CSCI) m major subdivisions q computer software components (CSC) q computer software units (CSU) l The WBS should include all software associated with the project regardless of whether it developed, furnished, or published Project CSCI CSC CSU Software WBS

37 Copyright SCRA 3737 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Size Estimation l Sizing By Analogy m Involves relating the proposed project to previously completed projects of similar application, environment and complexity m Basic Steps q Develop a list of functions and the number of lines of code to implement each function. q Identify similarities and differences between previously developed data base items and those data base items to be developed. q From the data developed in the previous steps, select those items which are applicable to serve as a basis for the estimate. q Generate a size estimate

38 Copyright SCRA 3838 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Size Estimation (Cont.) l Sizing by Program Evaluation and Review Technique (PERT) m Based on beta distribution and on separate estimation of individual software components m Calculation of standard deviation assumes that the estimates are unbiased toward either underestimation or overestimation m Experience shows that most likely estimates tend to cluster toward the lower limit, while actual software product sizes tend to cluster more toward the upper limit

39 Copyright SCRA 3939 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Size Estimation (Cont.) l Function Points m Method of estimating size during the requirements phase based on the functionality to be built into the system m General Approach q Count the number of inputs, outputs, inquiries, master files, and interfaces required. q Multiply these counts by the following factors: í Inputs - 4 í Outputs -5 í Inquires -4 í Master files -10 í Interfaces -7 q Adjust the total of these products +25%, 0, or -25% based on the programs complexity

40 Copyright SCRA 4040 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Reuse l Many software products consists of newly developed software and previously developed software m The previously developed software is adapted for use in the new product l Some effort is required to adapt existing software m Redesigning the adapted software to meet the objectives of the new product m Reworking portions of the code to accommodate redesigned features or changes in the new products environment m Integrating the adapted code into the new product environment and testing the resulting software product

41 Copyright SCRA 4141 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Effects of Software Reuse on Size Estimate l The effects of reuse are estimated by calculating the Equivalent Number of Source Lines of Code (ESLOC) l Basic Reuse Model where q ASLOC is the size of the adapted COTS software component expressed in thousands of adapted source lines of code q NSLOC is the size of new software component expressed in thousands of new source lines of code q DM is the percent design modified q CM is the percent code modified q IM is the percent of integration required for modified software

42 Copyright SCRA 4242 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Nonlinear Reuse Effects Usual Linear Assumption Data on 2954 NASA modules [BOEHM95] Relative Cost Amount of Reused Software Modified Copyright 1995, Baltzer Science Publishers. Used with permission.

43 Copyright SCRA 4343 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Nonlinear Reuse Model l Nonlinear reuse estimation model m where q SU is the software understanding increment which is expressed as a percentage (ranges from 10-50%). q AA deals with the degree of assessment and assimilation needed to determine whether a fully- reused software module is appropriate to the application and to integrate its description into the overall product description (ranges from 0-8%). q The remaining variables in the equation are the same as those used in the original COCOMO.

44 Copyright SCRA4 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Estimation Risks l Adverse effects due to inaccurate software estimation stems from an inability to accurately assess risks associated with various software development projects l Four major risk areas m Software project sizing m Specification of development environment m Assessment of staff skills m Definition of objectives, requirements, and specifications l All potential risks should be defined and weighed, and impacts to project cost should be determined

45 Copyright SCRA 4545 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Risk Example: Software Sizing Accuracy Versus Phase 0.25x 0.5x 0.67x 0.8x x 1.25x 1.5x 2x 4x FeasibilityPlans and requirements Product design Detailed Design Development and test Concept of operation Requirements specification Product design spec. Detailed Design Spec. Accepted Software Phases and Milestones Relative Size Range Completed Programs USAF/ESD Proposals + Size (SLOC) Cost ($) [BOEHM95] Copyright 1995, Baltzer Science Publishers. Used with permission.

46 Copyright SCRA 4646 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Use Several Independent Estimation Techniques l Techniques available for cost estimation m Expert Judgment m Analogy m Top-Down m Bottom-Up m Parametric or Algorithmic Models l Important to use a combination of techniques m None of the techniques are better than the others from all aspects m Their strengths and weaknesses are complementary

47 Copyright SCRA 4747 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Expert Judgment l These techniques involve consulting one or more experts, who use their experience and understanding of proposed project to arrive at and estimate l May utilize group consensus techniques m Compute median or mean of individual expert estimates m Group meeting m Delphi (iterative process) q Anonymous estimation q No group discussion m Wideband Delphi (iterative process) q Combines the free discussion advantages of the group meeting technique and the advantages of anonymous estimation

48 Copyright SCRA 4848 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Expert Judgment (Cont.) l Strengths m Able to factor in the differences between past project experiences and the new techniques, architectures, or applications of the future project m Can also factor in exceptional personnel characteristics and interactions, or other unique project considerations l Weaknesses m The estimate is no better than the expertise and objectivity of the estimator (biases, incomplete recall) m Difficult to strike balance between: q Quick response expert estimate í timely, efficient, but hard to calibrate and rationalize q Group consensus estimate í Soundly based but highly time consuming and not always exactly repeatable

49 Copyright SCRA 4949 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Estimation By Analogy l Reasoning by analogy with one or more completed projects to relate their actual costs to an estimate of the cost of a similar new project l Strengths m Useful when developing a new product when a systematic historical cost database does not exist m Based on actual experience on a project l Weaknesses m A high degree of judgment is required when making adjustments for differences in analogous products m Not clear to what degree the previous project is actually representative of the constraints, techniques, personnel, and functions to performed on the new project

50 Copyright SCRA 5050 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Top-Down Estimating l Overall cost estimate for the project is derived from the global properties of the software project l Cost is then split up among the various components l Can be done in conjunction with any of the before-mentioned methods l Strengths m System level focus m Efficient, easier to implement, requires minimal detail l Weaknesses m Can be less accurate due to lack of detail m Tends to overlook lower level components and possible technical problems

51 Copyright SCRA 5151 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Bottom-Up Estimating l The cost of each software component is estimated by an individual and these costs are then summed to arrive at an estimated cost for the overall product l Strengths m More detailed basis m More stable m Fosters individual commitment l Weaknesses m May overlook system level costs m Requires more effort

52 Copyright SCRA 5252 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Parametric Models l Mathematical expressions m Derived from the statistical correlation of historical system costs with performance and/or physical attributes of the system m Can produce high quality, consistent estimates if derived from a sound representative database l Focus on major cost drivers (not minute details) m Predominant effect on system costs m Independence (cost drivers are uncorrelated) l Strengths m Objective m Repeatable m Efficient m Facilitates sensitivity analysis

53 Copyright SCRA 5353 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP l Linear models l Multiplicative models l Analytic models l Tabular models m Contains tables which relate the values of cost driver variables to multipliers used to adjust the effort estimate l Composite models m Incorporate a combination of linear, multiplicative, analytic, and tabular functions to estimate software effort as a function of cost driver variables Parametric Models (Cont.)

54 Copyright SCRA 5454 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Information Needed to Use a Parametric Model l Well documented parameters identifying: m source of data used to derive the parametric model m size of database m time frame of database m range of database m how parameters were derived m limitations spelled out m how well the parametric model estimates its own database m consistent and well defined WBS dictionary l Well documented parameters identifying: m source of data used to derive the parametric model m size of database m time frame of database m range of database m how parameters were derived m limitations spelled out m how well the parametric model estimates its own database m consistent and well defined WBS dictionary l Realistic estimates of most-likely range for independent variable values l Top functional experts knowledgeable about the project being estimated m to identify most-likely range for cost drivers m to confirm applicability of parametric from technical perspective l Realistic estimates of most-likely range for independent variable values l Top functional experts knowledgeable about the project being estimated m to identify most-likely range for cost drivers m to confirm applicability of parametric from technical perspective

55 Copyright SCRA5 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design l Software Cost Estimation Process l Parametric Software Cost Models l Parametric Hardware Cost Models l Applications of Cost Modeling to the RASSP Design Process l Summary and Major Issues

56 Copyright SCRA 5656 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Example Parametric Software Cost Estimators l A number of automated software estimation tools are available which allow for quick effort and schedule estimates based on size estimates and cost driver attributes l 15 to 20 cost driver attributes that reflect the development environment depending on the model used l Examples m COCOMO m COCOMO 2.0 m REVIC ( REVised Intermediate COCOMO) m PRICE S Model m SEER-SEM m SASET

57 Copyright SCRA 5757 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Constructive Cost Model (COCOMO) l Hierarchy of software cost estimation models m Basic COCOMO q Estimates software development effort and cost solely as a function of the size of the software product in source instructions m Intermediate COCOMO q Estimates software development effort as a function of the most significant software cost drivers as well as size m Detailed COCOMO q Represents the effects of the cost drivers on each individual development cycle phase q Used during detailed phases of design to refine cost estimates

58 Copyright SCRA 5858 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP COCOMO (Cont.) l Models three modes of software development m Organic q Small-to-medium size product developed in a familiar, in-house environment m Embedded q Product must operate within tight constraints q Product is embedded in a strongly coupled complex of hardware, software, regulations, and operational procedures m Semidetached q Intermediate stage between organic and embedded mode q Team members have varied experience with related systems

59 Copyright SCRA 5959 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Summary of COCOMO Hierarchy of Models

60 Copyright SCRA 6060 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Intermediate COCOMO Model Software Development Time where l C - constant used to capture multiplicative effects on time with projects of increasing effort (DEFAULT = 2.5) l D - scale factor which accounts for the relative economies or diseconomies of scale encountered for projects of different required efforts (DEFAULT = 0.32) l PSCED - the percent compression/expansion to the nominal deployment schedule Software Development Time where l C - constant used to capture multiplicative effects on time with projects of increasing effort (DEFAULT = 2.5) l D - scale factor which accounts for the relative economies or diseconomies of scale encountered for projects of different required efforts (DEFAULT = 0.32) l PSCED - the percent compression/expansion to the nominal deployment schedule Software Development Effort where l KSLOC - software size in thousands of source lines of code l A - constant used to capture the multiplicative effects on effort with projects of increasing size (DEFAULT = 2.8) l B - scale factor which accounts for the relative economies or diseconomies of scale encountered for software projects of different sizes (DEFAULT = 1.2 -> diseconomy) l F i s - cost drivers which model the effect of personnel, computer, product, and project attributes on software cost Software Development Effort where l KSLOC - software size in thousands of source lines of code l A - constant used to capture the multiplicative effects on effort with projects of increasing size (DEFAULT = 2.8) l B - scale factor which accounts for the relative economies or diseconomies of scale encountered for software projects of different sizes (DEFAULT = 1.2 -> diseconomy) l F i s - cost drivers which model the effect of personnel, computer, product, and project attributes on software cost Embedded Mode Intermediate COCOMO Model l Costs including product design through the completion of the integration and test phase

61 Copyright SCRA 6161 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Software Cost Attributes (F i ) in Intermediate COCOMO l Computer Attributes m TIME - Execution Time Constraint m STOR - Main Storage Constraint m VIRT - Virtual Machine Volatility m TURN - Computer Turnaround Time l Product Attributes m RELY - Required Software Reliability m DATA - Database Size m CPLX - Product Complexity l Computer Attributes m TIME - Execution Time Constraint m STOR - Main Storage Constraint m VIRT - Virtual Machine Volatility m TURN - Computer Turnaround Time l Product Attributes m RELY - Required Software Reliability m DATA - Database Size m CPLX - Product Complexity l Project Attributes m MODP - Modern Programming Practices m TOOL - Use of Software Tools m SCED - Required Development Schedule l Personnel Attributes m ACAP - Analyst Capability m AEXP - Applications Experience m PCAP - Programmer Capability m VEXP - Virtual Machine Experience m LEXP - Programming Language Experience l Project Attributes m MODP - Modern Programming Practices m TOOL - Use of Software Tools m SCED - Required Development Schedule l Personnel Attributes m ACAP - Analyst Capability m AEXP - Applications Experience m PCAP - Programmer Capability m VEXP - Virtual Machine Experience m LEXP - Programming Language Experience

62 Copyright SCRA 6262 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Intermediate COCOMO (Cont.) FACTOR SELECTION Selected Candidate Factors (Wolverton, Doty, etc.) Surveyed Experts to Determine Which Factors Had: General Significance (Not Restricted To Special Cases) Independence (Not Correlated With Size, Other Factors) (EQUATION: MM = MM (Nom) X P where P = Product of 15 Attribute Numerical Ratings) FACTORS INCLUDED (and Ranges) RATINGS Product Attributes (Higher Ratings Increase Effort) VL LONMHIVH - Required Reliability (RELY) (1.87) Data Base Size, DB/KDSI (DATA) (1.23) Product Complexity (CPLX) (2.36) Computer Attributes (Higher Ratings Increase Effort) - Memory Constraints (STOR) (1.56) Timing Constraints (TIME) (1.66) Virtual Machine Volatility (VIRT) (1.49) Turnaround Time (TURN) (1.47) [FERENS]

63 Copyright SCRA 6363 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Intermediate COCOMO (Cont.) VL LONMHIVH Personnel Attributes (Higher Ratings Decrease Effort) - Analyst Capability (ACAP) (2.06) Programmer Capability (PCAP) (2.03) Applications Experience (AEXP) (1.57) Virtual Machine Experience (VEXP) (1.34) Language Experience (LEXP) (1.20) Project Attributes (Higher Ratings Decrease Effort Except SCED, Where All But NOM Increase Effort) - Modern Development Practices (MODP) (1.92) Use of Modern Tools (TOOL) (1.65) Schedule Effects (SCED) (1.23) FACTORS INCLUDED (and Ranges) RATINGS [FERENS]

64 Copyright SCRA 6464 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Calibrating Nominal Effort Equations (Cont.) l Calibrating the Software Development Mode m Use a similar least squares technique to calibrate the coefficient term c and the scale factor b in the effort equation m Given completed projects p 1,..., p n, solve for c and b which satisfy the following equations q where

65 Copyright SCRA 6565 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Intermediate COCOMO - Maintenance Estimate l Basic model assumption m Software maintenance costs are determined by substantially the same cost driver attributes that determine software development costs. m Annual maintenance effort equation where m ACT is the annual change traffic m (MM) NOM is the nominal software development effort which is only a function of the software size m F i is the maintenance effort adjustment factor for cost driver attribute i

66 Copyright SCRA6 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP SOFTWARE SUPPORT COSTS - COCOMO REVIC COCOMO II COCOMO-M Equation: MM A = MM NOM x ACT x P M MM A is Annual Person-Months MM NOM is Nominal Person-Months (From COCOMO) ACT is Annual Change Traffic (% Code Changed per Year) P M is Product of Maintenance Multipliers (SCED Not Used; RELY and MODP Values Change) Like COCOMO-M, Except (ONLY) 15-Year Support Costs Highest In Years 1 and 2, Then Steady-State Equation is MM M = A x Size M x P M MM M is Maintenance Man Months Size M = (Base Code Size) x MCF x MAF MCF = (Size Added + Size Modified) / Base Code Size MAF = 1 + ((SU/100)(UNFM)) [FERENS]

67 Copyright SCRA 6767 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Calibrating a Cost Model to a Particular Organization l Example: COCOMO calibration m Calibrating the COCOMO nominal effort equations to an organizations design experience q Calibrating the constant term q Calibrating the software development mode m Other calibration methods q Consolidating or eliminating redundant cost driver attributes within the model q Adding further cost driver attributes which may be significant at this organization, but not in general

68 Copyright SCRA 6868 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Calibrating Nominal Effort Equations l Calibrating the constant term "c" m Ex. Embedded mode m To calibrate to an organizations completed projects p 1,..., p n with q sizes: KSLOC 1, KSLOC 2,..., KSLOC n overall effort adjustment factors: F 1, F 2,..., F n q actual development efforts: MM 1, MM 2,..., MM n m Solve for the value of "c" which minimizes the sum of squares of residual errors

69 Copyright SCRA 6969 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP REVIC l REVIC (REVised Intermediate COCOMO) predicts software development life-cycle costs m Costs including requirements analysis through completion of software acceptance testing m Maintenance life-cycle costs for fifteen years l REVIC Software Development Modes

70 Copyright SCRA 7070 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP REVIC Development Phase Descriptions

71 Copyright SCRA 7171 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP REVIC Development Phase Descriptions (Cont.) l REVIC development equations predict effort and schedule from Preliminary Design through Integration & Test l REVIC predicts the effort and schedule in the Software Requirements Engineering and Development Test & Evaluation phases by taking a percentage of the development phases m Software Requirements Engineering (default values) q 12% of development effort q 30% of development schedule m Development Test & Evaluation (default values) q 22% of development effort q 26% of development schedule

72 Copyright SCRA 7272 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP REVIC Software Development Cost/Schedule Models Software Development Time where l C - constant used to capture multiplicative effects on time with projects of increasing effort (DEFAULT = 6.2) l D - scale factor which accounts for the relative economies or diseconomies of scale encountered for projects of different required efforts (DEFAULT = 0.32) l PSCED - the percent compression/expansion to the nominal deployment schedule Software Development Effort where l KSLOC - thousands of source lines of code l A - constant used to capture the multiplicative effects on effort with projects of increasing size (DEFAULT = 4.44) l B - scale factor which accounts for the relative economies or diseconomies of scale encountered for software projects of different sizes (DEFAULT = 1.2 -> diseconomy) l F i s - cost drivers which model the effect of personnel, computer, product, and project attributes on software cost Embedded Mode REVIC (REVised Intermediate COCOMO) Model l Predicts software development costs l Costs including requirements analysis through completion of software acceptance testing l Maintenance life-cycle costs for fifteen years

73 Copyright SCRA 7373 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Additional Project Attributes for REVIC

74 Copyright SCRA 7474 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP REVIC Maintenance Phase Description l REVIC estimates the maintenance of a software product over a fifteen year period l REVIC assumes the presence of a transition period after the delivery of the software m Residual errors are found before reaching a steady state condition providing a declining, positive delta to the ACT during the first three years m Maintenance Equation where m MM nom is the nominal development effort m ACT is the annual change traffic (default value = 15%) m MF i is the set of maintenance adjustment factors

75 Copyright SCRA 7575 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Differences Between REVIC and the Original COCOMO l REVIC utilizes an updated set of coefficients used in the basic effort and schedule equations m Calibrated using recently completed DOD projects l REVIC provides a single weighted average distribution for effort and schedule over the development phases m COCOMO provides a table for distributing the effort and schedule over the development phases l REVIC allows the user to vary the percentages in the system requirements engineering and DT&E phases l REVIC automatically calculates the standard deviation for each Computer Software Component (CSC) for risk assessment

76 Copyright SCRA 7676 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP COCOMO 2.0 Model l The original COCOMO and its successor, ADA COCOMO were well-matched to their target software projects m Largely custom, build-to-specification software l COCOMO has been experiencing increasing difficulty in estimating costs and schedules for software developed using new approaches, e.g. l Object-oriented software m Spiral or evolutionary development approaches m COTS and reuse-driven approaches l COCOMO 2.0 is was developed to address these limitations

77 Copyright SCRA7 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP COCOMO 2.0 Three-Stage Model Series l Application Composition Model m Supports prototyping efforts to resolve potential high-risk issues such as user interfaces, software/system interaction, performance, or technology maturity m Uses the number of object points as the sizing input l Early Design Model m Supports exploration of alternative software system architectures and concepts of operation m Not enough information is generally available for fine-grain cost estimation during the early stages of the software project m Uses the number of function points as the sizing input m Utilizes 7 cost driver attributes l Post-Architecture Model m Same granularity as previous COCOMO and ADA COCOMO m Utilizes 17 effort multipliers

78 Copyright SCRA 7878 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP COCOMO 2.0 Development Effort Estimates l Nominal Person Months l COCOMO 2.0 Scaling Approach m Scale factors W i represent the rating for the following scale drivers: q Precedentedness q Development Flexibility q Architecture/Risk Resolution q Team Cohesion q Process Maturity

79 Copyright SCRA 7979 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Breakage Percentage l COCOMO 2.0 uses a breakage percentage to adjust the effective size of the product based on the requirements volatility in a project. l Breakage Percentage m The percentage of code thrown away due to requirements volatility l COCOMO 2.0 adjustment (not used in Application Composition) m where q BRAK is the breakage percentage

80 Copyright SCRA 8080 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP COCOMO 2.0 Re-engineering and Conversion Estimation l Additional refinement is needed to estimate the costs of software re-engineering or conversion l COCOMO 2.0 re-engineering and conversion approach m where q AT is the percentage of the code that is re- engineered by automatic translation. q ATPROD is the productivity for automatic translation in source statements/person month.

81 Copyright SCRA 8181 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Post-Architecture Model Effort and Schedule Estimates l Adjusting Development Effort (Person-Months) l Development Schedule Estimates l Output Ranges m Optimistic Estimate: 0.80(PM adjusted ) m Pessimistic Estimate: 1.25(PM adjusted )

82 Copyright SCRA 8282 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Comparison of COCOMO and COCOMO 2.0

83 Copyright SCRA 8383 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Summary of SW Cost Estimators

84 Copyright SCRA 8484 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design l Software Cost Estimation Process l Parametric Software Cost Models l Parametric Hardware Cost Models l Applications of Cost Modeling to the RASSP Design Process l Summary and Major Issues

85 Copyright SCRA 8585 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ASIC Cost/Schedule Estimation l Paraskevopoulos and Fey showed that VLSI design schedules are a function of only one parameter: m ASIC development effort (person-months) l Development effort is a function of organizational productivity and design complexity (gates per IC) l VLSI schedule models are similar to the software schedule models developed by Boehm l VLSI design classifications m full custom m cell based m standard cells m gate arrays

86 Copyright SCRA 8686 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Full Custom ASIC Cost Equation l Basic ASIC effort equation m where q M is the ASIC development effort in person-months q D is the average annual improvement factor q A is the startup manpower q B is a measure of productivity q YR is ( current year) q H is the economy or diseconomy of scale q Size is the equivalent number of transistors

87 Copyright SCRA 8787 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Full Custom Design Complexity Calculation l Computation of equivalent number of transistors l Size equation

88 Copyright SCRA8 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Full Custom Design Parameter Values l Design effort model parameter values

89 Copyright SCRA 8989 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Gate Array ASIC Design Productivity l Basic gate array productivity model m where q G is the number of gates used in thousands l More detailed gate array productivity model m where q I is the adjusted number of I/Os [ (I/O) 0.5 /K gates q U is the maximum of percentage of gates used minus 90% and 0 q R is the complexity rating on a scale of 1 to 5 q D is the number of previous designs completed by the designer [FP89] © IEEE 1989

90 Copyright SCRA 9090 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Gate Array Design Cost l Gate array development effort (person-weeks) m where q M is the development effort in person-months q P can be the detailed or basic productivity values l Example: m Using basic productivity model q Development effort is proportional to an exponent of the number of gates

91 Copyright SCRA 9191 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ASIC Schedule Equations l Basic ASIC schedule equation m where q M is the development effort in person-months q h is the model coefficient q g is the economy/diseconomy of scale l ASIC schedule models

92 Copyright SCRA 9292 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP FPGA vs. ASIC Design Costs l Typical cost values for a 10,000 gate ASIC (gate array) or FPGA design

93 Copyright SCRA 9393 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP FPGA vs. ASIC Development Time l Typical schedule for a 10,000 gate design

94 Copyright SCRA 9494 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Commercial ASIC Hardware Models l PRICE-M m Produces estimates of development and production costs/schedule for ASICs and electronic modules (MCMs) m Uses parametric cost estimates based: q number of transistors/gates q percentage of new circuit cells and design repeat q specification level q degree of computer-aided design q product familiarity and engineering experience l SEER-IC m Estimates integrated circuit & multi-chip module development and manufacturing costs m Utilizes industry wide knowledge bases

95 Copyright SCRA 9595 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design l Software Cost Estimation Process l Parametric Software Cost Models l Parametric Hardware Cost Models l Applications of Cost Modeling in the RASSP Design Process l Summary and Major Issues

96 Copyright SCRA 9696 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Classifications of Design and Test Methodologies l Methodology I: m Standard COTS - Minimum Hardware Cost l Methodology II: m COTS with Cost Modeling - Minimum System Cost l Methodology III: m Full Custom - Custom Hardware plus Software l Methodology IV: m COTS with Cost Modeling and Virtual Prototyping l Methodology V: m COTS with Cost Modeling, Virtual Prototyping, and Use of Advanced Top-Down Programming Methodologies and Reuse

97 Copyright SCRA 9797 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Modeling-Based Front-End Design Approach Form Factor Constraints Performance Requirements Memory/ Communication Requirements APPLICATION REQUIREMENTS Functional Requirements Software Reuse Library Performance Benchmarks Schedule Constraints Manpower Constraints COTS Processor-Memory Board Prices COTS Processor-Memory Board Form Factor Ratings Labor Rates Software Size SW Development Cost Driver Attribute Ratings Expected Product Revenue Production Volume Expected Product Lifetime SYSTEM-LEVEL COST PARAMETERS Estimated Communication Overhead Cost-Driven Architecture Selection Task Assignment Task Scheduling Performance Modeling HW/SW Architectural Candidates Executable Requirement

98 Copyright SCRA 9898 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Case Study: SAR Multiprocessor l SAR Processor is required to form images in real-time on board an F-22 or an unmanned air vehicle (UAV) l Pulse Repetition Frequency Hz m Delivers 512 pulses in 0.92 seconds m Each pulse contains 4064 data samples for each of four polarizations l Processor must be able to form a 512-pulse image for each of three polarizations in real-time m Maximum latency is 3 seconds l Computational Requirement Gflop/sec l Memory Requirement - 77 MB

99 Copyright SCRA9 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP SAR Algorithm: Single Polarization Input Data Barker Detect Header Decode Form Aux Form Signal Video-to-Baseband Equalization Weight Range DFT Form Frame Load I/Q Coeffs Load Equalization Weights Load RCS Weights Form Processing Array Azimuth DFT Kernel Multiplication Azimuth IDFT Output Data Load Convolutional Kernels Setup Function DATA PREP

100 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Functional Decomposition Video-to-Baseband I/Q Even (8-tap FIR) I/Q Odd (8-tap FIR) Range DFT 1024 pt FFT 1024 Butterflies Azimuth DFT/iDFT 256 pt FFT 512 Butterflies 256 pt FFT 512 Butterflies

101 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP SAR System-Level Cost Parameters

102 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP SAR Software Cost Driver Ratings STEP 1STEP 2

103 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Automated Cost-Driven Architecture Design (RACEWAY) Schedule Constraints Schedule Constraints Power/Size Constraints Power/Size Constraints Real-time Constraints Real-time Constraints Functional Requirements (Function blocks) Functional Requirements (Function blocks) Communication Requirements (Data volumes of communications) Communication Requirements (Data volumes of communications) Cost-driven Architecture Design Engine (CADE) Cost-driven Architecture Design Engine (CADE) 17 HH-FORM_FRAME HH-PROC_ARRAY HH-256_FFT3 18 HH-256_FFT1 HH-512_BUTT1 HH-512_BUTT2 19 VH-256_FFT2 20 VH-I256_FFT4 VH-I512_BUTT1 VH-I512_BUTT2 21 VH-KERN_MULT VH-I256_FFT2 22 VH-256_FFT4 VH-512_BUTT1 VH-512_BUTT2 23 VH-I256_FFT1 24 VH-PROC_ARRAY VH-256_FFT1 25 VH-I256_FFT3 26 VH-256_FFT3 27 VH-FORM_FRAME VV-I256_FFT2 28 VV-256_FFT3 VV-512_BUTT1 VV-I512_BUTT2 29 VV-256_FFT4 30 VV-I256_FFT3 VV-I512_BUTT1 31 VV-FORM_FRAME VV-PROC_ARRAY VV-256_FFT2 32 VV-512_BUTT2 VV-I256_FFT1 33 VV-256_FFT1 34 VV-KERN_MULT VV-I256_FFT4 Results from SAR Benchmark Conceptual Design Processor Type Board Type Number of Processor Boards SHARC 2_PROC 1 SHARC 4_PROC 8 Total Number of Processors: Total Memory Capacity: Mbytes Processor Utilization: 0.71 Memory Utilization: 0.58 Time-to-market: months Total Life Cycle Cost($M): 4.31 Architecture Sizing Model Solution Time: 7.81 sec Assignment of Tasks to Processor Architecture Processor Index Tasks Assigned HH-DATA_PREP HH-IQ_ODD 2 HH-1024_FFT1 HH-1024_FFT2 HH-1024_BUTT HH-RCS 3 HH-IQ_EVEN HH-EQUALIZE 4 VH-1024_FFT1 VH-1024_FFT2 VH-1024_BUTT VH-RCS 5 VH-IQ_ODD VH-EQUALIZE 6 VH-DATA_PREP VH-IQ_EVEN 7 VV-1024_FFT1 VV-1024_BUTT VV-RCS 8 VV-DATA_PREP VV-1024_FFT2 9 VV-IQ_EVEN VV-EQUALIZE 10 VV-IQ_ODD 11 HH-I256_FFT4 HH-I512_BUTT1 HH-I512_BUTT2 12 HH-KERN_MULT HH-I256_FFT2 13 HH-256_FFT4 14 HH-I256_FFT3 15 HH-256_FFT2 16 HH-I256_FFT1 EE Issues System Engineering Issues System Engineering Issues System-level Cost Parameters

104 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP SAR Architectural Profiles

105 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP SAR Benchmark Cost Analysis

106 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology II over I

107 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology II over I (Cont.)

108 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology II over I (Cont.)

109 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology II over III

110 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology IV over I

111 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology IV over III

112 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology V over I

113 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Cost Improvement: Methodology V over III

114 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction to Cost Modeling-Based Embedded Systems Design l Software Cost Estimation Process l Parametric Software Cost Models l Parametric Hardware Cost Models l Applications of Cost Modeling to the RASSP Design Process l Summary and Major Issues

115 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Summary l This module demonstrated the cost-effectiveness system- level design methodologies that incorporate cost modeling l In practice, system engineering (SE) drives EE design m Front-end SE typically involves less than 4% of the total prototyping time and cost, but accounts for over 70% of a projects life cycle cost l Cost models, often organization-specific for maximum accuracy, are most effective if used to drive early system design m No specific cost model or objective function is recommended for use by all sectors of the electronics industry m These cost models can only be developed and refined through historical information collected within the specific industry sectors m Cost models can be integrated into the EE aspects of the design process in a seamless manner

116 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Summary (Cont.) l The focus of this module was on requirements of the SE/EE interface as opposed to the specification l The SAR case study demonstrated: m how modern design and test methodologies can benefit from the automated use of cost models early on in the design process m the relationship between time-to-market/cost with the system architecture m an order of magnitude improvement in cost-related objective functions l Parametric cost estimators have recently been used in industry with a great deal of success m SEER was used on Motorolas Iridium project, one largest and most complex software projects ever m The tool appears to have estimated software development cost within 3% of project actuals

117 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP References l [AHRENS95] J. Ahrens, N. Prywes, Transition to a Legacy- and Reuse-Based Software Life Cycle, IEEE Computer, pp , Oct. 1995; © IEEE 1995 l [AF94] U.S. Air Force Analysis Agency, REVIC Software Cost Estimating Model Users Manual Version 9.2, Dec l [AND95] J. Anderson, Projecting RASSP Benefits, Proc. Second Annual RASSP Conf., ARPA, US Dept. of Defense, Arlington, VA l [BOEHM81] B. Boehm, Software Engineering Economics, Prentice-Hall, Inc. Englewood Cliffs NJ, l [BOEHM88] B. Boehm, A Spiral Model of Software Development and Enhancement, IEEE Computer, pp , May 1988; © IEEE 1988 l [BOEHM95] B. Boehm, et al., Cost Models for Future Software Processes: Cocomo 2.0, Annals of Software Engineering, 1995, Baltzer Science Publishers. Used with permission. l [COCOMO] COCOMO manual, University of California, l [DEB97] J. DeBardelaben, V. Madisetti, A. Gadient, The Economics of Design & Test of COTS- based Embedded Microelectronics Systems, IEEE Design & Test of Computers, Fall l [DOANE93] D. Doane, P. Franzon, Multichip Module Technologies and Alternatives -The BASICS, Van Nostrand Reinhold, l [DOD95] Department of Defense, Parametric Cost Estimating Handbook, Fall l [FERENS] Class notes from Dr. Daniel Ferens. Used with permission.

118 Copyright SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP References (Cont.) l [FEY85] C. Fey, Custom LSI/VLSI Chip Design Productivity, IEEE Journal of Solid-State Circuits, Vol. sc-20, No. 2, April 1985, pp l [FP89] C. Fey, D. Paraskevopoulos, Studies in VLSI Technology Economics IV: Models for Gate Array Design Productivity, IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, August 1989, pp ; © IEEE 1989 l [IEEE] All referenced IEEE material is used with permission. l [LEVITT92] M. Levitt, Economic and Productivity Considerations in ASIC Test and Design-for- Test, Digest of Papers: Compcon 92, pp , Spring l [LIU95] J. Liu, Detailed Model Shows FPGAs True Costs, EDN, pp , May 11, l [MAD95] V. Madisetti, T. Egolf, Virtual Prototyping of Embedded Microcontroller-Based DSP Systems, IEEE Micro, Oct l [MAD96] V. Madisetti, Rapid Digital System Prototyping: Current Practice, Future Challenges, IEEE Design & Test of Computers, Fall 1996, pp ; © IEEE 1996 l [MINK95] A. Minkiewicz, A. DeMarco, The PRICE Software Model, PRICE Systems Internal Document, June l [PF87] D. Paraskevopoulos, C. Fey, Studies in LSI Technology Economics III: Design Schedules for Application-Specific Integrated Circuits, IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 2, April 1987, pp l [Richards97] Richards, M., Gadient, A., Frank, G., eds. Rapid Prototyping of Application Specific Signal Processors, Kluwer Academic Publishers, Norwell, MA, 1997 l [SEPO96] Software Engineering Process Office (SEPO), NCCOSC RDTE DIV, Software Size, Cost, and Schedule Estimation Process Version 2.0, March l [ZUERN94] B. Zuerndorfer, G. Shaw, SAR Processing for RASSP Application, Proc. 1st Annual RASSP Conf., pp , Arlington, VA, August 1994.


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