1. ARM Assembly Language Programming

2. Data Processing Instructions
ARM data processing instructions enable the programmer to perform arithmetic and logical operations on data values in registers.
All other instructions just move data around and control the sequence of program execution, so the data processing instructions are the only instructions which modify data values.

3. Data Processing Instructions
Here are some rules which apply to ARM data processing instructions:
All operands are 32 bits wide and come from registers or are specified as literals in the instruction itself.
The result, if there is one, is 32 bits wide and is placed in a register. (There is an exception here: long multiply instructions produce a 64-bit result)
Each of the operand registers and the result register are independently specified in the instruction. That is, the ARM uses a '3-address' format for these instructions.

4. Data Processing Instructions
Categories:
Data Movement Between Registers
Arithmetic instructions
Logical Instructions
Comparison Instructions

5. Data Movement Between Registers
MOVE Instructions:
MOV –
Move a 32-bit value into a register Rd. This instruction loads a 32-bit value into the destination register, from another register, a shifted register or an immediate value.
Ex:
MOV R1,R0 ;R1R0
MOV R1,R0,LSL #2 ;R1R0 * 4
MOV R1,#1 ;R1 0X
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x0004
STOP B STOP
END

6. Data Movement Between Registers
MOVE Instructions:
MVN –
Move the NOT of the 32 bit value into a register Rd.
Ex:
MVN R1,R0 ;R1 NOT R0
MVN R1,R0,LSL #2 ; R1 NOT (R0 * 4)
MVN R0,#4 ;R0 NOT 4
After movement original contents of source register will remain same.
AREA RESET,CODE,READONLY
ENTRY
START
MVN R1,#0x0004
STOP B STOP
END

7. Arithmetic Instructions
The arithmetic instructions are used to do the operations of addition and subtraction of 32-bit signed and unsigned values.
ADD –
The instruction will add the two operands, placing the result in the destination register. Operand 1 is a register, operand 2 can be a register, shifted register or an immediate value.
Ex:
ADD R0,R1,R2 ;R0 R1+R2
ADD R0,R1,#234 ;R0R1+234
ADD R0,R2,R3,LSL #1 ;R0R2+(R3<<1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R0,#0x0004
MOV R1,#0x0008
ADD R2,R1,R0
STOP B STOP
END

8. ADC R0,R2,R3,LSL #1 ;R0R2+(R3<<1)+C
The instruction will add the two operands along with the carry flag, placing the result in the destination register. It uses carry bit, so can add numbers larger than 32-bits. Operand 1 is a register, operand 2 can be a register, a shifted register or an immediate value.
Ex:
ADC R0,R1,R2 ;R0 R1+R2+C
ADC R0,R1,#234 ;R0R1+234+C
ADC R0,R2,R3,LSL #1 ;R0R2+(R3<<1)+C
AREA RESET,CODE,READONLY
ENTRY
START
MOV R0,#0x0004
MOV R1,#0x0008
ADC R2,R1,R0
STOP B STOP
END

9. R3R1+R2, R3=1FFFFFFFE, Hence C=1
ADDS –
The instruction will add the two operands, placing the result in the destination register. It updates the flags such as N,V,Z,C. Operand 1 is a register, operand 2 can be a register, a shifted register or an immediate value.
Ex:
ADDS R0,R1,R2 ;R0 R1+R2
ADC R5,R3,R1 ;R5R3+R1+C
Let R1=0xFFFFFFFF
R2=0XFFFFFFFF
R3R1+R2, R3=1FFFFFFFE, Hence C=1
AREA RESET,CODE,READONLY
ENTRY
START
MOV R0,#0xFFFFFFFF
MOV R1,#0xFFFFFFFF
ADDS R2,R1,R0
ADC R3,R2,R1
STOP B STOP
END

10. SUB R0,R2,R3,LSL #1 ;R0R2-(R3<<1)
The instruction will subtract the operand2 from operand1, placing the result in the destination register. Operand 1 is a register, operand 2 can be a register, shifted register or an immediate value.
Ex:
SUB R0,R1,R2 ;R0 R1-R2
SUB R0,R1,#234 ;R0R1-234
SUB R0,R2,R3,LSL #1 ;R0R2-(R3<<1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R0,#0x0008
MOV R1,#0x0004
SUB R2,R0,R1,LSL #1
STOP B STOP
END

11. SBC(Subtraction with carry) –
The instruction will subtract the two operands along with the carry flag, placing the result in the destination register. It uses carry bit to represent ‘borrow’, so can subtract numbers larger than 32-bits. SUB and SBC generate the carry flag the wrong way around, if a borrow is required then the carry flag is UNSET. Thus, this instruction requires a NOT Carry Flag-it inverts the flag automatically during the instruction. Operand 1 is a register, operand 2 can be a register, a shifted register or an immediate value.
Ex:
SBC R0,R1,R2 ;R0 R1-R2- NOT C
SBC R0,R1,#234 ;R0R NOT C
SBC R0,R2,R3,LSL #1 ;R0R2-(R3<<1)-NOT C

12. SUBS R0,R1,R2 ;R0 0XFFFFFFFC, C-0 SBC R3,R0,#2 ; R30XFFFFFFF9, C-0
The instruction will subtract the two operands, placing the result in the destination register. It updates the flags such as N,V,Z,C. Operand 1 is a register, operand 2 can be a register, a shifted register or an immediate value.
Ex:
SUBS R0,R1,R2 ;R0 R1-R2
SBC R5,R3,R1 ;R5R3-R1- NOT C
EX: MOV R1,#04
MOV R2,#08
SUBS R0,R1,R2 ;R0 0XFFFFFFFC, C-0
SBC R3,R0,#2 ; R30XFFFFFFF9, C-0
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#04
MOV R2,#08
SUBS R0,R1,R2
SBC R3,R0,#2
STOP B STOP
END

13. RSB (Reverse Subtraction) –
It is used to reverse subtract of two 32-bit values. The instruction will subtract operand1 from operand2, placing the result in the destination register. In normal subtraction operand2 is subtracted from operand1. Operand 1 is a register, operand 2 can be a register, a shifted register or an immediate value. Normally this instruction is used for negating or 2’s complementing of numbers.
Ex:
RSB R0,R1,R2 ;R0 R2-R1
RSB R0,R1,#234 ;R0234-R1
RSB R0,R2,R3,LSL #1 ;R0(R3<<1)-R2
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x02
MOV R2,#0x08
RSB R0,R1,R2
STOP B STOP
END
R0R2-R1

14. Ex: RSB R0,R1,R2 ;R0 R2-R1 Let R1=0X00000000 R2=0X00000033
Result R0=0x x
R0=0xffffffcd
R0=-33 (negation of 33)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x01
MOV R2,#0x00
RSB R0,R1,R2
STOP B STOP
END
R0R2-R1; 2’s complement of 1 is FFFFFFFF

15. RSC (Reverse Subtraction with carry) –
It is used to reverse subtract with carry of two 32-bit values. The instruction will subtract operand1 from operand2 and complemented value of carry, placing the result in the destination register. In normal subtraction operand2 is subtracted from operand1. Operand 1 is a register, operand 2 can be a register, a shifted register or an immediate value.
Ex:
RSC R0,R1,R2 ;R0 R2-R1-NOT C
RSC R0,R1,#234 ;R0234-R1-NOT C
RSC R0,R2,R3,LSL #1 ;R0(R3<<1)-R2- NOT C
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x02
MOV R2,#0x04
SUBS R0,R1,R2
RSC R3,R1,R2
STOP B STOP
END
Result:
R0R1-R2 ; 0xFFFFFFFE0x02-0x04
R3R2-R1-NOT C ; 0x 0x04-0x02-0x01

16. Logical Instructions
Logical Instructions perform bitwise logical operations on the two source registers.
The logical instructions update the CPSR flags only if the S sufix is present.
These instructions can use barrel-shifted second operands in the same way as the arithmetic instructions.

17. It does logical bitwise AND of two 32-bit values.
Flags updated if S is used are : N,Z,C
This instruction will perform a logical AND operation between two operands, placing the result in the destination register. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Ex:
AND R0,R1,R2 ;R0 R1 AND R2
AND R0,R1,#0x ;R0R1 AND 0x
AND R0,R2,R3,LSL #1 ;R0R2 AND (R3<<1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x02
MOV R2,#0x04
AND R0,R1,R2
STOP B STOP
END
Result:

18. It does logical bitwise OR of two 32-bit values.
ORR –
It does logical bitwise OR of two 32-bit values.
Flags updated if S is used are : N,Z,C
This instruction will perform a logical OR operation between two operands, placing the result in the destination register. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Ex:
ORR R0,R1,R2 ;R0 R1 AND R2
ORR R0,R1,#0x ;R0R1 AND 0x
ORR R0,R2,R3,LSL #1 ;R0R2 AND (R3<<1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x0A
MOV R2,#0x05
ORR R0,R1,R2
STOP B STOP
END

19. It does logical bitwise XOR of two 32-bit values.
EOR –
It does logical bitwise XOR of two 32-bit values.
Flags updated if S is used are : N,Z,C
This instruction will perform a logical XOR operation between two operands, placing the result in the destination register. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Ex:
EOR R0,R1,R2 ;R0 R1 AND R2
EOR R0,R1,#0x ;R0R1 AND 0x
EOR R0,R2,R3,LSL #1 ;R0R2 AND (R3<<1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x0A
MOV R2,#0x05
EOR R0,R1,R2
STOP B STOP
END

20. BIC R0,R2,R3,LSL #1 ;R0R2 AND ~(R3<<1)
This instruction will perform logical AND operation between operand 1 and complemented value of operand 2. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Ex:
BIC R0,R1,R2 ;R0 R1 AND ~ R2
BIC R0,R1,#0x ;R0R1 AND ~(0x )
BIC R0,R2,R3,LSL #1 ;R0R2 AND ~(R3<<1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x0A
MOV R2,#0x05
BIC R0,R1,R2
STOP B STOP
END

21. Comparison Instructions
Comparison instructions are used to compare or test a register with a 32-bit value.
They update CPSR flag bits according to the result, but do not affect other registers.
After the bits have been set, the information can then be used to change program flow by using conditional execution.
Suffix S is not required to update the flags in case of comparison instructions.

22. CMP (Compare)–
The CMP instruction performs subtraction, but does not store result. The flags are updated. CMP allows to compare the contents of a register with another register or an immediate value, updating the status flags to allow conditional execution to take place. The flags refer to operand1 compared against operand2. Thus, GT suffix will be executed if operand1 is greater than operand2. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Flags updated: N,Z,V,C
Ex:
CMP R0,#1 ;Z=1 if R0=1, N=0 if R0>1
CMP R0,R1 ;Z=1 if R0=R1, N=0 if R0>R1
CMP R0,R2,LSL #1 ;Z=1 if R0=(R2,LSL #1), N=0 if R0>(R2,LSL #1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R1,#0x0A
MOV R2,#0x05
CMP R1,R2
BNE NEXT
MOV R3,0xFF
STOP B STOP
NEXT MOV R4,0xFF
STP B STP
END

23. CMN (Compare Negated)–
The CMN is same as CMP, except it allows to compare against small negative values (the logical NOT of operand2). This is used in application such as -1 to end a list. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Flags updated: N,Z,V,C
Ex:
CMN R0,#1 ;Z=1 if R0=-1,
CMP R0,R1 ;Z=1 if R0=-R1,
CMP R0,R2,LSL #1 ;Z=1 if R0=(R2,LSL #1)
AREA RESET,CODE,READONLY
ENTRY
START
MOV R0,#0x00
LOOP
CMN R0,#1
BNE NEXT
MOV R3,#0xFF
STOP B STOP
NEXT
SUB R0,#1
B LOOP
STP B STP
END

24. TST (Test)–
This instruction performs a non-destructive AND (the result is not stored). It performs Logical AND operation between operand1 and operand2 without storing the result, but only the flags are always updated.
The most common use of this instruction is to determine the value of an individual bit of a register. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Operand 1 is the data word to test and operand 2 is a bit mask. After testing the Zero flag will be set upon a match, or otherwise clear.
Flags updated: N,Z,C

25. TST (Test)–
Ex:
MOV R1,#0x0004
MOV R2,#0X0001
TST R1,R2
R1 : (operand1)
R2 : (operand2)
Result : Z=1, as 0th Bit of R1 is Zero.

26. TEQ (Test Equivalence) –
This instruction performs a non-destructive bit-wise XOR (the result is not stored). It performs Logical XOR operation between operand1 and operand2 without storing the result, but only the flags are always updated.
The most common use of this instruction is to determine if two operands are equal without affecting the V flag. It can also be used to identify if two values have the same sign, since the N flag will be the logical XOR of the two sign bits. Operand 1 is a register, operand 2 can be register, shifted register, or an immediate value.
Flags updated: N,Z,C

27. TEQ (Test Equivalence)–
Ex:
MOV R1,#0x0004
MOV R2,#0X0004
TEQ R1,R2 ;Z=1 if R1=R2

28. Multiply Instructions
The multiply instructions multiply the contents of a pair of registers and depending upon the instructions, accumulate the results in another register.
The long multiplies accumulate onto a pair of register or a pair of registers.
The final result is placed in a destination register or a pair of registers.
The number of cycles taken to execute a multiply instruction depends on the processor implementation.
For some implementations the cycle timing also depends on the value in Rs.

29. MUL Multiply 32 bit result
MLA Multiply and accumulate 32 bit result
These two instructions are different from the normal arithmetical instructions in that there are restrictions on the operands, namely:
All operands, and the destination, must be given as simple registers.
You cannot use immediate values or shifted registers for operand two.
The destination and operand one must be different registers.
Lastly, you cannot specify R15 as the destination.

30. Flags updated if S used: N,Z (C- unpredictable) Ex: MUL R2,R1,R0
MUL (Multiply) –
This instruction performs a 32*32 multiply operation, and stores a 32-bit result. Since only the least significant 32 bits are stored, the result is the same for signed and unsigned numbers.
Flags updated if S used: N,Z (C- unpredictable)
Ex: MUL R2,R1,R0
Let R0=0x , R1=0x
R2=0x
Result: R2=0x

31. Flags updated if S used: N,Z (C - unpredictable)
MLA (Multiply And Accumulate) –
MLA behave that same as MUL, except that the value of operand three is added to the result. This is useful for running totals.
Flags updated if S used: N,Z (C - unpredictable)
This instruction performs a 32*32 multiply operation, then stores the sum of Rn and the 32-bit multiplication result to Rd. Since only the least significant 32 bit of the multiplication are used, the result is the same for signed and unsigned numbers.

32. EX:
MLA R3,R2,R1,R0 ;R3=(R1xR2)+R0
The instruction adds the product of R1 and R2 to R0 and stores the result in R3.

33. A MAC Unit
In addition to the barrel shifter, the ARM7 has a built in Multiply Accumulate Unit (MAC).
The MAC supports integer and long integer multiplication.
The integer multiplication instructions support multiplication of two 32-bit registers and place the result in a third 32-bit register.
A multiply-accumulate instruction will take the same product and add it to a running total.
Long integer multiplication allows 32-bit quantities to be multiplied together and the 64-bit result is placed in two registers.

34. A MAC Unit
The mnemonics used in the operation of multiplication are as follows.
Mnemonic
Function
Result
MUL
Multiply
32-bit
MULA
Multiply Accumulate
UMULL
Unsigned Multiply
64-bit
UMLAL
Unsigned Multiply Accumulate
SMULL
Signed Multiply
SMLAL
Signed Multiply Accumulate

35. MUL R4,R2,R1 ;R4=R2*R1
MULS R4,R2,R1 ;R4=R2*R1, THEN SET THE FLAGS
MLA R7,R8,R9,R3 ;R7=R8*R9+R3
SMULL R4,R8,R2,R3 ;R4=BITS OF R2*R3
;R8=BITS OF R2*R3
UMULL R6,R8,R0,R1 ;{R6,R8}=R0*R1
SMLAL R4,R8,R2,R3 ;R4=BITS OF R2*R {R4,R8}
;R8=BITS OF R2*R3+{R4,R8}
UMLAL R6,R8,R0,R1 ;{R6,R8}=R0*R1+{R6,R8}

36. Data Transfer Instructions
Data transfer instructions move data between ARM registers and Memory.
There are three basic forms of data transfer instructions in the ARM instruction set.
Single Register Load and Store Instructions
Multiple register load and store instructions
Single register swap instructions.

37. Single register Load and Store
These instructions are used for moving a single data item in and out of a register. The data types supported are signed and unsigned words (32-bit), half words (16-bit), and bytes. Here are the various load-store single-register transfer instructions.
LDR
Load word into a register
Rd<- mem32[address]
STR
Save byte or word from a register
Rs-> mem32[address]
LDRB
Load byte into a register
Rd<-mem8[address]
STRB
Save byte from a register
Rs->mem8[address]

38. LDRH
Load halfword into a register
Rd<- mem16[address]
STRH
Save halfword from a register
Rs-> mem16[address]
LDRSB
Load signed byte into a register
Rd<-sign Extended mem8[address]
LDRSH
Load signed halfword into a register
Rd<-sign Extend mem16[address]

39. Single register load-store addressing modes
The ARM instruction set provides different modes for addressing memory. These modes incorporate one of the indexing methods: preindex with writeback, preindex, and postindex
Index Method
Data
Base address register
Example
Preindex with
writeback
Mem[base+offset]
Base+offset
LDR r0,[r1,#4]!
Preindex
Not updated
LDR r0,[r1,#4]
Post index
Mem[base]
LDR r0,[r1],#4
Note: ! Indicates that the instruction writes the calculated address back to the base address register.

40. LDR: Load Register LDR R0,[R1] 0A 00 0B 01 06 02 09 03 80 04 05 88 56
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 05 88 56 07
R0=0x
R1=0x
After
LDR R0,[R1]
R0=0x
R1=0x

41. LDRH: Load Half Word LDRH R0,[R1] 0A 00 0B 01 06 02 09 03 80 04 22 05
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
R0=0x
R1=0x
Half Word
After
LDRH R0,[R1]
R0=0x
R1=0x
Zero Extended bits[31:16]

42. LDRB: Load Register Byte LDRB R0,[R1]
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
R0=0x
R1=0x
Byte
After
LDRH R0,[R1]
R0=0x
R1=0x
Zero Extended bits[31:8]

43. LDRSB: Load Register Signed Byte LDRSB R0,[R1]
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
R0=0x
R1=0x
Byte
After
LDRSB R0,[R1]
R0=0xFFFFFF 80
R1=0x
Sign Extended bits[31:8]

44. LDRSH: Load Register Signed Halfword LDRSH R0,[R1]
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
R0=0x
R1=0x
Byte
After
LDRSH R0,[R1]
R0=0xFFFF 2280
R1=0x
Sign Extended bits[31:16]

45. STR: Store Register STR R0, [R1,#4] 0A 00 0B 01 06 02 09 03 80 04 22
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
Let
R0=0x
R1=0x
STR R0,[R1,#4] ;memory[R1+4]=R0, R1 unchanged

46. After
STR R0, [R1,#4]
Memory Locations 0A 00 0B 01 06 02 09 03 44 04 33 05 22 11 07
R0=0x
R1=0x
Memory=[R1+4]
=0x
R1=0x
R0=0x
R1=0x
STR R0,[R1,#4] ;memory[R1+4]=R0, R1 unchanged

47. STRB: Store Register Byte STRB R0, [R1,#4]
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
Let
R0=0x
R1=0x

48. After
STRB R0, [R1,#4]
Memory Locations 0A 00 0B 01 06 02 09 03 44 04 33 05 22 11 07
R0=0x
R1=0x
Memory=[R1+4]
=0x
R1=0x
Byte
R0=0x
R1=0x

49. STRH: Store Register Halfword STRH R0, [R1,#2]
Memory Locations 0A 00 0B 01 06 02 09 03 80 04 22 05 88 56 07
Let
R0=0x
R1=0x
STRH R0,[R1,#2] ; memory[R1+2]=R0, R1 unchanged

50. After
STRH R0, [R1,#2]
Memory Locations 0A 00 0B 01 44 02 33 03 80 04 22 05 88 06 56 07
R0=0x
R1=0x
Memory=[R1+2]
=0x
R1=0x
Half word
R0=0x
R1=0x
STRH R0,[R1,#2] ; memory[R1+2]=R0, R1 unchanged

51. LDR Different Addressing Modes
Instruction
R0=
R1+=
Preindex with
writeback
LDR R0,[R1,#0X04]
Mem32[R1+0x04]
0x04
LDR R0,[R1,R2]!
Mem32[R1+R2] R2
LDR R0,[R1,R2,LSR#0x04]!
Mem32[R1+(R2 LSR 0x04)]
(R2 LSR 0x04)
Preindex
LDR R0,[R1,#0x04]
Not updated
LDR R0,[R1,R2]
LDR R0,[R1,-R2,LSR #0x4]
Mem32[R1-(R2 LSR 0x04)]
Postindex
LDR R0,[R1],#0x4
Mem32[R1]
0x4
LDR R0,[R1],R2
LDR R0,[R1],R2,LSR #0x4
(R2 LSR 0x4)

52. Multiple Register Load & Store
Load-store multiple instructions can transfer multiple registers between memory and the processor in a single instruction.
The transfer occurs from a base address register Rn pointing into memory.
Multiple-register transfer instructions are more efficient from single-register transfers for moving blocks of data around memory and saving and restoring context and stacks.

53. Multiple Register Load & Store
Load-store multiple instructions can increase interrupt latency.
ARM implementations do not usually interrupt instructions while they are executing.
For example, on an ARM7 a load multiple instruction takes 2 + Nt cycles, where N is the number of registers to load and t is the number of cycles required for each sequential access to memory.
If an interrupt has been raised, then it has no effect until the load-store multiple instruction is complete.

54. Addressing Mode for Load-Store Multiple Instruction
LDM – Load Multiple Registers
STM – Store Multiple Registers
Addressing Mode for Load-Store Multiple Instruction
Addressing
Mode
Description
Start Address
End Address
Rn! IA
Increment After Rn
Rn+4*N-4
Rn+4*N IB
Increment Before
Rn+4 DA
Decrement After
Rn-4*N+4
Rn-4*N DB
Decrement Before
Rn-4

55. LDM – Load Multiple
The LDM instruction permits block moves of memory to the registers and enables efficient stack operations.
The registers may be listed in any order, but the registers are always loaded in order with the lowest numbered register getting value from the lowest memory address.
The addressing mode field determines how next address is calculated, which control how the address is updated in conjunction with each register load.

66. STM – Store Multiple
The STM instruction permits block moves of registers to memory and enables efficient stack operations.
The registers may be listed in any order, but the registers are always stored in order with the lowest numbered register going to the lowest memory address.

71. Stack Operations using STM and LDM
Stack is a data structure, which usually is a LIFO(last in first out) queue.
Data is pushed onto the top of stack, and also popped from the top of the stack, where the processor adjusts the stack pointer before and after each operation.
ARM processors have a stack pointer, register r13, which holds the address of either the next empty entry or the last filled entry in the queue, depending on what type of stack you have.

72. Stack Operations using STM and LDM
A full stack is one where the stack pointer points to the last used (full) location.
An empty stack is one where the stack pointer points to the next available (empty) stack location.
As well a stack can grow through increasing memory address (ascending) or downwards through decreasing memory addresses(descending).

73. Forms of stack
Full ascending: the stack grows up through increasing memory addresses and the base register points to the highest address containing a valid item. (post decrement (DA) on pop.
Empty ascending: the stack grows up through increasing memory addresses and the base register points to the first empty location above stack.(pre decrement (DB) on pop)

74. Forms of stack
Full descending: the stack grows down through decreasing memory addresses and the base register points to the lowest address containing a valid item. (post-increment (IA) on pop)
Empty descending: the stack grows down through decreasing memory addresses and the base register points to the first empty location above stack. (pre increment on (IB) pop)

75. There are a number of load-store multiple addressing mode aliases available to support stack operations.
Addressing Mode
Description
POP
=LDM
PUSH
=STM FA
Full ascending
LDMFA
LDMDA
STMFA
STMIB FD
Full descending
LDMFD
LDMIA
STMFD
STMDB EA
Empty ascending
LDMEA
LDMDB
STMEA
STMIA ED
Empty Descending
LDMED
LDMIB
STMED
STMDA

76. STMFD: pushes registers onto the stack, updating the Stack Pointer (ie R13).
Example:
Let
R1=0x
R4=0x
R13=0x
STMFD R13!,{R1,R4}

77. LDMFD: pops registers from the stack, updating the Stack Pointer (ie R13).
Example:
Let
R13=0x c
LDMFD R13!,{R1,R4}
Result:
R1=0x
R4=0x
R13=0x

78. STMED: pushes registers onto the stack, but updates register SP to point to the next empty location
Example:
Let
R1=0x
R4=0x
R13=0x
STMED R13!,{R1,R4}

79. SWP: Swap Instruction
The swap instruction exchanges a word between registers and memory as one atomic instruction.
This prevents crucial data exchanges from being interrupted by an exception.
The SWP instruction exchanges a word between a register and memory.
The SWP instruction also allows to exchange the contents of two registers.
Example:
SWP R0,R1,[R2] ;R0=[R2]
;[R2]=R1
;R1=Unchanged
AREA RESET,CODE,READONLY
ENTRY
START
LDR R2,=0X
LDR R3,=0X
STR R3,[R2]
LDR R0,=0x
LDR R1,=0X
SWP R0,R1,[R2] ;[R2]<--R1, R0<--[R2], R1-unchanged
STP B STP
END

80. SWI-Software Interrupts
SWIs are generated by using the ARM instruction SWI.
It causes an exception to be taken, and forces the processor into Supervisor mode, which is privileged.
When an SWI instruction is encountered, the processor fetches the instruction at the exception vector address 0x after changing to Supervisor mode.

81. Control Flow Instructions
The third category of instructions neither processes data nor moves it around; it simply determines which instructions get executed next.
Branch Instructions:
The basic branch instruction allows a jump forward or backward of up to 32MB.
The branch instructions has several forms.
The branch link instruction jumps to the destination and stores a return address in R14(link register).
By using condition codes we can perform conditional branching and conditional calling of functions.

82. B:Branch
B is the simplest branch. Upon encountering a B instruction, the ARM processor will jump immediately to the address given, and resume execution from there.
Example: B LABEL
. . .
LABEL

83. Conditional Branches
If we want the processor to take a decision whether or not to branch, we use conditional branch instruction.
Ex:
MOV R0,#0
LOOP
ADD R0,R0,#1
CMP R0,#10
BNE LOOP
. . .

84. Branch Interpretation Normal Uses
BAL
Unconditional
Always
Always take this branch
BEQ
Equal
Comparison equal or zero result
BNE
Not Equal
Comparison not equal or non-zero result
BPL
Plus
Result positive or zero
BMI
Minus
Result minus or negative
BCC
BLO
Carry clear
Lower
Arithmetic operation did not give carry out
Unsigned comparison gave lower
BCS
BHS
Carry Set
Higher or same
Arithmetic operation gave carry out
Unsigned comparison gave higher or same

85. Branch Interpretation Normal Uses
BVC
Overflow clear
Signed integer operation; no overflow occurred
BVS
Overflow set
Signed integer operation; overflow occurred
BGT
Greater Than
Signed integer comparison gave greater than
BGE
Greater or equal
Signed integer comparison gave greater or equal
BLT
Less than
Signed integer comparison gave less than
BLE
Less or equal
Signed integer comparison gave less than or equal
BHI
Higher
Unsigned comparison gave higher
BLS
Lower or same
Unsigned comparison gave lower or same

86. Conditional execution
Conditional execution applies not only to branches but also to the ARM instructions.
Example:
CMP R0,#5
BEQ BYPASS
ADD R1,R1,R0
SUB R1,R1,R2
BYPASS
These instructions can be replaced by

87. Conditional execution
CMP R0,#5
ADDNE R1,R1,R0
SUBNE R1,R1,R2
. . .
Conditional execution is invoked by adding 2-letter condition after the 3-letter opcode.

88. Branch and Link
A common requirement in a program is to be able to branch to a subroutine in a way which makes it possible to resume the original code sequence when the subroutine has completed.
This requires that a record is kept of the value of the program counter just before the branch is taken.
ARM offers this functionality through the branch and link instruction which, as well as performing a branch in exactly the same way as the branch instruction, also saves the address of the instruction following the branch in the link register, r14:

89. It performs a subroutine call.
BL: Branch with Link
Link register R14 is loaded with the contents of R15(PC) just before the branch.
R14 is reloaded into R15(PC) to return to the instruction after the branch.
The branch with link or BL, is similar to B instruction but overwrites the link register LR with a return address.
It performs a subroutine call.
AREA RESET,CODE,READONLY
ENTRY
START
BL ADDITION ;BRANCH TO ADDITION SUBROUTINE
CMP R2,#08
MOVEQ R2,#0
STP B STP
ADDITION ;ADDITION SUBROUTINE
ADD R1,R2,#4
MOV PC,LR ;RETURN FROM SUBROUTINE BY MOVING PC=LR
END

90. Bx: Branch, AND OPTIONALLY EXCHANGE
The BX instruction is used to branch to a target address stored in a register based on an optional condition.
If bit 0 of the register is set to 1, then the processor will switch to Thumb execution.
AREA RESET,CODE,READONLY
ENTRY
MOV R0,#5
ADD R1,PC,#1 ;LOAD ADDRESS OF ;SUB_BRANCH, SET FOR THUMB ADDITING 1
BX R1 ;R1 CONTAINS ADDRESS OF ;SUB_BRANCH+1
;ASSEMBLER SPECIFIC INSTRUCTION TO SWITCH TO ;THUMB
SUB_BRANCH
BL THUMB_SUB
ADD R1,#7 ;POINT TO SUB_RETURN WITH BIT ;CLEAR
BX R1 ;ASSEMBLER SPECIFIC INSTRUCTION TO ;SWITCH TO ARM
SUB_RETURN
THUMB_SUB
MOV R2,#4
MOV PC,LR
END

91. ADD R1,PC,#1 ;LOAD ADDRESS OF ;SUB_BRANCH, SET FOR THUMB ADDITING 1
MOV R0,#5
ADD R1,PC,#1 ;LOAD ADDRESS OF ;SUB_BRANCH, SET FOR THUMB ADDITING 1
BX R1 ;R1 CONTAINS ADDRESS OF ;SUB_BRANCH+1
;ASSEMBLER SPECIFIC INSTRUCTION TO SWITCH TO ;THUMB
SUB_BRANCH:
BL THUMB_SUB
ADD R1,#7 ;POINT TO SUB_RETURN WITH BIT ;CLEAR
BX R1 ;ASSEMBLER SPECIFIC INSTRUCTION TO ;SWITCH TO ARM
SUB_RETURN
Listing 1 shows one example (not the only one) of using the BXinstruction to go from ARM to Thumb state and back. This example first switches to Thumb state, then calls a subroutine that was written in Thumb code. Upon return from the subroutine, the system again switches back to ARM state; though this assumes that R1 is preserved by the subroutine. ThePC always contains the address of the instruction that is being executed plus 8 (which happens to be SUB_BRANCH). The Thumb BL instruction actually resolves into two instructions, so 8 bytes are used between SUB_BRANCH and SUB_RETURN.
When an exception occurs, the processor automatically begins executing in ARM state at the address of the exception vector. So another way to change state is to place your 32-bit code in an exception handler. If the CPU is running in Thumb state when that exception occurs, you can count on it being in ARM state within the handler. If desired, you can have the exception handler put the CPU into Thumb state via a branch.

92. BLX: Branch with Link, optionally exchange instruction set
An unconditional branch with link to a program relative address
A conditional branch with link to an absolute address held in a register.

93. ADR - Instruction
Load a program-relative or register-relative address into a register. ADR always assembles to one instruction.
The assembler attempts to produce a single ADD or SUB instruction to load the address.
ADR produces position-independent code, because the address is program-relative or register-relative.