1. Network-on-Chip Paradigm Erman Doğan

2. OUTLINE SoC Communication Basics  Bus Architecture  Pros, Cons and Alternatives NoC  Why NoC?  Components  Characteristics Topology Routing Switching Strategy On-Chip vs Off-Chip Networks

3. Introduction Network-on-a-chip (NoC) is a new approach to System-on-Chip (SoC) design. NoC-based systems can accommodate multiple asynchronous clocking that many of today's complex SoC designs use. The NoC solution brings a Networking method to on- chip communication and brings notable improvements over conventional bus systems.

4. SoC Communication Basics Shared Medium:  Common Buses, Data Paths. Hybrid Networks:  Hierarchical buses, Multiple Backplane.  Local communication on shared bus, packet switched network on higher levels. Direct and Indirect Network:  Presence of Network Interface Block  P2P communication support

5. On-Chip Buses On-chip Bus design  Bus topology, mapping  Bus data transmission Bus segment widths, DMA size, data packet size  Bus control Priorities Basic operation  Arbitration of accesses to the shared bus  Data transfer

6. On-Chip Buses - Advantages Easy Design Low Cost Good utilization

7. On-Chip Buses - Disadvantages Energy Inefficiency Non scalable Bandwidth. Everyone on the bus had to talk at the same speed. Central arbitration is a bottleneck Long wire delays – Clock skews Long wire capacitative disadvantages, crosstalk noises

8. Solutions and Alternatives Regular architecture – Instead of irregular global wiring Point to Point Communication – Enables multiple connection, distribution of load Packet Based Communication GALS – Globally Asynchronous and Locally Synchronous

9. The SoC nightmare The architecture is tightly coupled Source: Prof Jan Rabaey CS-252-2000 UC Berkeley DMACPUDSP Mem Ctrl. Bridge MPEG Ioo The “Board-on-a-Chip” Approach C System Bus Control Wires Peripheral Bus

10. On-chip Communication Bus based interconnect  Low cost  Easier to Implement  Flexible Networks on Chip  Layered Approach  Buses replaced with Networked architectures Better electrical properties Higher bandwidth Energy efficiency Scalable Irregular architectures Regular Architectures Bus-based architectures

11. Why NoC? Physical Nanometer-Technology Effects Better Scalability Chip Design Productivity Gap Distributed Nature of Modern Chip Architectures

12. Why NoC? Physical Nanometer-Technology Effects Decreasing wire dimensions increases resistance. Decreasing inter-wire spacing increases capacitance, wire coupling delays, and crosstalk noises. Today’s long wires (including bus lines) require the periodic insertion of repeaters. NoC favors the use of short wires and the overall reduction of the total wire length in the chip. NoC builds a highly-utilized and shared interconnection network with short links connected by routers.

13. Why NoC? Chip Design Productivity Gap It is a common assumption that the productivity of the designer increases every year by 21%, while the design complexity increases by 58% (following Moore’s Law). It calls for the development of highly reusable modules and the availability of third party IP cores. The module’s interface should be independent of the chip size and of the number of modules on the chip.

14. Why NoC? Chip Design Productivity Gap Moore’s Law Progress in Design Automation MOORE’S LAW The capacity of integrated chips doubles every 18-20 months. Time 65 75 80 85 90 95 2000 10 8 1 10 6

15. Why NoC? Distributed Nature of Modern Chip Architectures The next generation of chip designs will incorporate multiple autonomous intelligent modules with a rich collection of communication services among them. The level of parallelism in chips is on the rise.

16. NoC Components Network adapters implement the interface by which cores (IP blocks) connect to the NoC. Their function is to decouple computation (the cores) from communication (the network). Routing nodes route the data according to chosen protocols. They implement the routing strategy. Links connect the nodes, providing the raw bandwidth. They may consist of one or more logical or physical channels.

17. NoC Characteristics Topology Routing Techniques Switching Strategy

18. NoC Characteristics Topology The network topology refers to the static arrangement of channels and nodes in the network. A good topology allows to fulfill the requirements of the traffic at reasonable costs. Network topology can be compared with a network of roads.

19. NoC Characteristics Topology - Examples 1D Mesh Ring 2D Mesh Butterfly Fat tree Torus

20. NoC Characteristics Routing Routing is the task of finding a path from a source node to a destination node on a given topology. Routing is one of the key components that determine the performance of the network. Objectives of a routing algorithm:  Reduce the number of hops and overall latency  Balance the load of network channels

21. NoC Characteristics Switching Strategy Switching strategy defines the way resources are allocated to the packets transfered across the chip. Two common strategies:  Circuit Switching  Packet Switching

22. NoC Characteristics Switching Strategy – Circuit Switching A bufferless flow control Channels are reserved to form circuits for transmissions No packet dropping No misrouting of packets

23. NoC Characteristics Switching Strategy – Packet Switching No reserved path, non-deterministic routes Packet can take any path to the destination Non-deterministic delay due to buffer and congestion No QOS guarantee Flow and congestion control needed Packet switching is more popular in NoC literature

24. NoC Characteristics Switching Strategy – Packet Routing Schemes Store And Forward  After A finishes receiving the entire packet, A asks B if B is ready for the entire packet.  B → A, ack  A sends the packet to B.

25. NoC Characteristics Switching Strategy – Packet Routing Schemes Virtual Cut-Through  While A receives a part of the packet, A asks B if B is ready for the entire packet.  B → A, ack  A starts to send the packet to B even when A has not yet received the entire packet.

26. NoC Characteristics Switching Strategy – Packet Routing Schemes Wormhole  Wormhole flow control operates like cut-through.  The major difference is that cut-through flow control allocates buffers and channel bandwidth on a packet level, while wormhole flow control does this on the flit level.

27. “On-Chip” vs “Off-Chip” Networks Routers on Planar Grid Topology Short PTP Links between routers More predictable link delays

28. “On-Chip” vs “Off-Chip” Networks No legacy protocols to be compliant with No software  simple and hardware efficient protocols Different operating environment (no dynamic changes and failures) Custom Network Design – You design what you need! Replace Example1: Replace modules

29. “On-Chip” vs “Off-Chip” Networks Traffic Patterns:  Poisson distribution in large scale networks  More predictable in embedded systems  Pre-Scheduling increases the speed of transmissin and actual bandwidth

30. THANK YOU! Erman Doğan