1. Multi-bunch Feedback System Review and Challenges for 1-2GHz Japan Synchrotron Radiation Research Institute (JASRI) SPring-8 T. Nakamura CFA Beam Dynamics Mini Workshop on Low Emittance Rings 2011, 2011-10-05

2. Collective Effect Study at SPring-8 Calculation of Impedance of Beam Pipe Components by MAFIA Instability Simulation Based on the estimated Impedance with Home made Codes CISR : Coupled-bunch Instability Simulation (C++) SISR : Single-Bunch Instability Simulation http://www.spring8.or.jp/pdf/en/ann_rep/95/p157-158.pdf http://www.spring8.or.jp/pdf/en/ann_rep/95/p159-160.pdf http://www.spring8.or.jp/pdf/en/ann_rep/95/p161-162.pdf http://acc-physics.kek.jp/SAD/SAD2006/Doc/Slide/Nakamura.pdf Observation of CSR http://www.pasj.jp/web_publish/pasj2009pubfinal/papers/wpbta05.pdf Resistive-Wall Impedance of ID shielded by Cu Sheet http://accelconf.web.cern.ch/accelconf/p01/PAPERS/TPPH129.PDF Observation of Fast Ion Instability and Cure by gap in Bunch Trains http://accelconf.web.cern.ch/accelconf/p01/PAPERS/TPPH127.PDF Cure of Transverse Instabilities by Chromaticity Modulation http://accelconf.web.cern.ch/accelconf/p95/ARTICLES/WAC/WAC14.PDF http://accelconf.web.cern.ch/AccelConf/IPAC10/papers/thobra02.pdf http://acc-web.spring8.or.jp/~nakamura

3. Feedback * Detect Oscillation by Beam Position Monitor (BPM) * Calculate the Kick to Damp its Oscillation * Drive Kicker with Power Amplifier Multi-bunch Feedback (Bunch-by-bunch Feedback) * Suppression of Instabilities * Fast Damping of Oscillation excited by Injection perturbation Bunch-by-bunch Feedback (BBF) Control Oscillation Bunch-by-bunch ( independently ) Digital : ADC, DAC sampling rate = bunch rate ( f B ) Required Frequency in baseband (kicker amplifier) ~ f B /2 * BBF Processor with FPGA based 508MS/s Processor (world first?) => SPring-8, PF, TLS, SOLEIL, SSRF, HLS, PLS (PLS-II), and several ion rings. * Simultaneous suppression of 10mA/bunch mode-coupling insta. + 0.05mA/bunch train multi-bunch Insta.

4. BPM Kicker Storage Ring f B : Bunch rate 500MHz -> 2GHz DAC sampling rate f B ADC sampling rate f B Position History (Turn-by-turn) for Each Bunches Digital Feedback Processor FPGA Kick Signal Position Signal AB A-B Digital Bunch-by-bunch Feedback System ~ f B / 2 180 deg. hybrid Power Amp. FIR filter Front End Kick for Each Bunches

5. FIR Filter (Digital Signal Processing) Position History (Turn-by-turn) Kick FIR filter

6. Current Turn Output = Kick Input = Bunch Position (turn-by-turn) y0y0 x -1 -90 deg Phase Shift HOW? FIR filter Number of Taps FIR filter in FPGA x -2 x -3 0-2-3-4-5-6-7-8-9 Turn No

7. 9-tap FIR Filter for SPring-8 Storage Ring 9 Position History => Feedback Kick Larger Taps Smaller Noise Power Narrower Tune Acceptance.... Number of Taps > One Period For Smaller Noise Power Phase vs. Tune Gain vs. Tune FIR filter coefficients a k Q H Q V Q H T. Nakamura, et al. http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

8. 2GHz system for CLIC DR Higher frequency (Design) 2 GHz 4 x 500MHz ( SPring-8 ) Smaller beam size (Design) 2 um( β = 5m) 1/2 x 5um ( SPring- 8 ) Stronger Damping (Assumption, 1/10 x τ Radiation ) 0.2 ms 1/2 x 0.5 ms( SPring-8 ) Noise effect on Beam Size 4 x 2 x 2 ~ One order Higher than SP8

9. BPM Kicker DAC sampling rate f B ADC sampling rate f B Position History (Turn-by-turn) for Each Bunches Kick for Each Bunches Digital Feedback Processor Digital Signal Process Kick Signal Position Signal AB A-B Digital Bunch-by-bunch Feedback System ~ f B / 2 180 deg. hybrid Power Amp. Front End Storage Ring f B : Bunch rate 500MHz -> 2GHz FIR filter

10. Front-End RF Direct Sampling and Baseband Sampling

11. Front-End RF Direct Sampling and Baseband Sampling : 500MHz Down Conversion Baseband Sampling 180 deg hybrid ∆ ∆ = A-B A B ADC Bandwidth > 250MHz 30kHz 250MHz 30 kHz ~ 250 MHz Baseband signal 500MHz ± 30kHz BPM Signal ∆ 250MHz ~ 750 MHz Direct Sampling (SPring-8) ADC Wide Bandwidth > 1.5 f RF = 750MHz 500MHz LPF ~ 300MHz T. Nakamura, et al., http://cern.ch/AccelConf/e08/papers/thpc128.pdf 0.5 f B – 1.5 f B 1/2 f B ~ f B f B ± 1/2 f B 500 ± 250MHz

12. Front-End RF Direct Sampling and Baseband Sampling : 2 GHz ADC : ~ 3 GHz 180 deg hybrid ∆ ∆ = A-B A B ADC : ~ 1GHz 2 GHz Direct Sampling Down Conversion Baseband Sampling 30kHz Baseband signal ~2 GHz 2GHz ± 1GHz BPM Signal ∆ 1 GHz ~ 3 GHz tens kHz ~ 1 GHz LPF ~ 1.5 GHz NS ADC12D1800RF (2.8GHz(-3dB)) ~ f B f B – 1.5f B 1GHz 0.5 f B

13. Front-End RF direct sampling * Less Components => Less tuning points * High Frequency requires Wide bandwidth of ADC suffers Large noise by ADC sampling jitter Baseband Sampling * More Components * Low Frequency Smaller effect of ADC sampling jitter Jitter of Mixing signal (500MHz, 2GHz) is small Square Wave Mixing * More Components * Much LOWER Frequency http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

14. BPM Kicker DAC sampling rate f B ADC sampling rate f B Position History (Turn-by-turn) for Each Bunches Kick for Each Bunches Digital Feedback Processor Digital Signal Process Kick Signal Position Signal AB A-B Digital Bunch-by-bunch Feedback System ~ f B / 2 180 deg. hybrid Power Amp. FIR filter Front End Storage Ring f B : Bunch rate 500MHz -> 2GHz

15. Digital Feedback Processor FPGA ( Field Programmable Gate Array ) User Reconfigurable Hardware Logic Fast Parallel Low cost

16. Digital Bunch-by-bunch Feedback System ADC sampling timing Signal Divider fBfB ADC Digital Feedback Processor BPM Kicker Storage Ring DAC Multiplexer FIR Front End SPring-8 Processor (2004) tested/installed at ~ten storage rings f B / 4 (<300MHz) FPGA AB A-B ~500 ns f B : Bunch rate Harmonics = 4n http://accelconf.web.cern.ch/AccelConf/ica05/proceedings/pdf/P3_022.pdf

17. Digital Bunch-by-bunch Feedback System fBfB De- Multiplexer ADC DAC Multiplexer FIR Digital Feedback Processor BPM Kicker Front End AB A-B FPGA f B / 4 (<300MHz) with Recent Fast ADC fBfB Storage Ring f B : Bunch rate Harmonics = 4n Dimtel

18. Bunch-by-bunch Feedback System for 2GHz BPM Kicker Storage Ring 2GHz : Bunch rate Harmonics = 12n ( 2652 = 12 x 7 x 13 x 17) 167 MHz AD9739A 2GS/s DAC AB A-B DAC Multiplexer 1GS/s Multiplexer Xilinx Virtex-6/7 FIR De- Multiplexer De- Multiplexer De- Multiplexer De- Multiplexer 1, 13, 2, 14, 5, 17, 6, 18, NS ADC12D1800 Power Divider 1GS/s ADC Front End De- Multiplexer De- Multiplexer 2GS/s ADC 500MHz FPGA 12-bit

19. Bunch-by-bunch Feedback System for 2GHz FPGA BPM Kicker Storage Ring 2GHz : Bunch rate Harmonics = 8n 250MHz FIR AB A-B 2GS/s ADC 500MHz NS ADC12D1800 Multiplexer 1GS/s Multiplexer 1GS/s ADC De- Multiplexer De- Multiplexer Xilinx Virtex-6/7 De- Multiplexer De- Multiplexer De- Multiplexer De- Multiplexer 1, 9, 5, 13, 2, 10, AD9739A 2GS/s DAC DAC Multiplexer Front End 14-bit 12-bit Power Divider

20. Step size = 0.25 um Acceptance = 1mm (+/- 0.5mm) ADC resolution (How many bits ?) Step size << Beam size 2um (CLIC DR), 5um (SP8) Acceptance < Maximum Amplitude 0.2 – 0.3 mm for SPring-8 by Injection perturbation Acceptance 1 mm (+/- 0.5mm) Beam size : 2um ~ noise level Step size : 0.25um Maximum Amplitude for SPring-8 0.2-0.3 mm But Noise is much larger than step size

21. Digital Feedback Processor for 2GHz Required Specifications and Candidates ADC Bandwidth> 3 GHz for RF Direct Sampling > 1 GHz for Baseband Sampling NS ADC12D1800RF DAC Sampling Rate> 2 GS/s Bandwidth> 1 GHz Analog Devices AD9739A FPGA FIR filter > 167 MHz( 2GHz / 12 ) Xilinx Virtex-6/7 CLIC Pre-Damping Ring bunch rate2GHz,Harmonics 2652 = 12 x 13 x 17 baseband RF direct

22. Effect of Noise Excitation of Betatron motion Noise => Feedback System => Kicker < 1/10 of Beam Sizes Increase Effective Beam Size

23. Noise Sources Beam Position Monitor Noise Thermal noise Amplifier Noise by AD sampling Sampling Jitter ADC, BPM signal timing jitter, … Position Resolution

24. Revolution Freq. T 0 4.8 µs Total Damping Time τ  ~ τ FB  0. 5 ms Amplitude σ x < 0.1 x Beam Size 5 µm Position Resolution σ δ = 10σ x <   m for one passage Residual oscillation excited by Noise KickerFeedbackBeam High Position Resolution is required T. Nakamura, et al., EPAC’04, http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf T. Nakamura, NanoBeam ’05, http://atfweb.kek.jp/nanobeam/files/proceeding/proc-WG3b-12.pdf http://beam.spring8.or.jp/nakamura/papers/Nanobeam05/proc-WG3b-12.pdf Residual Oscillation Excited by Noise SPring-8 x  + δ Noise in Position Signal (BPM resolution, AD conversion, … )

25. Position Resolution σ δ = 2µm for one passage Residual Oscillation Excited by Noise E ~ 3GeV, C ~ 400m, T 0 = 1.3 µs Ver. Emittance ε V 1 pm ( Norm. 5 nm) Rad. Damping Time τ β 2 ms Feedback Damping Time τ  ~ τ FB  = 0.2 ms ~ 0.1 x τ β Allowable Amplitudeσ x < 0.1 x Beam Size σ V ~ 0.1 σ δ CLIC Damping Ring Beam size (Ver.) σ V 2 um ( β V = 5m) Just the assumption

26. ADC Performance on Noise ADC Noise Level < σ δ < 2 um (DR) Acceptance < 1 mm (+/- 0.5mm) Maximum Amplitude 0.2 – 0.3 mm for SPring-8 by Injection perturbation ADC S/N ratio > 1 mm / 2 um = 500 = 54 dB σ x ~ 0.1 σ δ < 0.1 x Beam size : 2 um (DR) Position Resolution

27. * The most of noise comes from Jitter of ADC clock * SNR in spec. sheets is defined for almost full swing signal For feedback, it’s Residual Signal it might be possible to keep small => lower SNR than Spec sheet SNR 76 dB 0 73 dB 77 dB 50 dB 60 dB 75 dB 74 dB 300MHz Input Frequency SNR Baseband RF direct Input Frequency 0 3 GHz2 GHz1 GHz AD 9467-250 (16bit, 250MS/s, 60fs jitter ) ADC12D1800RF (12bit, 2GS/s, 0.2 ps jitter) ADC S/N ratio (SNR) > 54 dB

28. ADC Noise by Sampling Jitter ADC Sampling Timing Jitter Ext. Clock, ADC inside, … ∆τ∆τ ∆x = x 2πf ∆τ Noise can be reduced by reducing Residual Signal Noise x Residual Signal In A-B

29. Residual Signal at input to ADC and Jitter of ADC Sampling => Noise

30. BPM Difference Signal Create Difference Signal (A-B) of Two BPM Electrodes (A,B) By adjusting Signal Level and Timing Open or Short End (100 % Reflection) BPM 0.1dB/step = 1%/step BPM 180 deg. Hybrid A B ADC A-B 1% ~ 100um

31. Residual Signal of BPM at ADC Input Reflections at Connections <= uncontrollable Shape Difference of BPM Electrodes => Bad Cancelation at 180 deg. Hybrid => Residual Signal Attenuator ~ 1%/step A-B 2ns 6dB BPM Open or Short End (100 % Reflection) Reflection 180 deg. Hybrid A B 1GHz BW 4GHz BW BPM signal 40mm (bad BPM)

32. Residual Signal and Jitter of ADC Sampling => Noise ∆x= +160μm ( 0 dB ) 2ns ADC Sampling Timing (-0.2dB = -2%) ∆x = -160μm 80μm BPM A-B Signal to ADC Noise by Sampling Jitter σ δ =  x (rms) ∆x∆x by reflection... (0.2dB = 2%) Residual Signal T. Nakamura, K. Kobayashi, and Z. Zhou, http://cern.ch/AccelConf/e08/papers/thpc128.pdf 6dB BPM A B A-B 180 deg Hybrid = 0.003 for 1 GHz = 0.009 for 3 GHz = 0.25 μm for 1 GHz = 1.8 μm for 3 GHz OK for 2GHz ADC Sampling Timing Jitter ADC A-B σ δ <  m BaseBand RF direct ∆τ = 0.5 ps (rms) Noise x=200μm for 3GHz = 2πf∆τ x= 80 μm for 1GHz

33. High Resolution Beam Position Monitor For SPring-8 0.2 nC bunch ( 100mA x 2 ns ) one passage of 2ns separation (wide band) σ δ = 10σ x <   m

34. High Resolution BPM by Shorted Stripline Structure Beam 20 mm 45 mm V H σ δ = σ V = 5  m Almost OK for <   m 1/4 part x 10 higher Resolution than Button BPM T. Nakamura, http://accelconf.web.cern.ch/AccelConf/d05/PAPERS/POW027.PDF for Ne /bunch =1.2×10 9 one passage (1/3.4 of CLIC DR)

35. Beam Position Monitor for 2 GHz * Many BPMs for High Resolution Measurement (reduction of noise) to achieve < 2um resolution for one passage Smaller Size for Fast Response (high frequency) Lower signal level => Worse Resolution Reduction of Beam Pipe bore Resolution~ 1/(bore) 2 Sensitivity ( ∆V/V)/∆x ~1/(bore) Reduction of Noise by Residual Signal Cutoff < 3 GHz (TE modes) BPM at high beta for large beam size

36. Kicker

37. Kick by sin wave input = Field Strength x Kicker Length x F = Reduction Factor for sin wave input Kick to the bunch = Integral of 2L/c period t 2L/c Input t = 0 L Bunch t = L/c Bunch Kicker Effective Length Kicker Transit Time Factor and Effective Length Transit Time Factor

38. Effective Length L = 0.3m L = 0.15m L = 0.075m 2L/c =2 x 0.3m/c = 1/500MHz t For 1GHz ( f B = 2GHz) Many Short ( ~ 0.075m ) Kickers are required for 1 GHz ( f B = 2GHz ) Kicker Transit Time Factor and Effective Length at High Beta for smaller number or lower amplifier power

39. 90x40 -1 V E x = 8V/m E y = 8V/m 0 V Diagonal Kicker E x = 9 V/m E y = 18 V/m -1 V 0 V -1V 70x40 E x = 19 V/m E y = 8V/m -1 V 0 V Orthogonal Kicker B Orthogonal Kicker C Orthogonal Kicker A 90x40 Stripline Kickers in SPring-8 90x40 E y = 12V/m E x = 16 V/m -1 V 0V -1V SUS Cu SUS Length 30cm Length 30cm Length 7cm Length 40 cm

40. Power Amplifier for Kicker * Frequency : a few tens kHz – 1 GHz AR, R&K,... * Kick Strength ~ Amplitude of beam (injection,... ) x Feedabck Damping Time Kicker Power ~ (Kick Strength ) 2 Reduce Amplitude of beam

41. YES : Multi-bunch Feedback For 2GHz is Possible with Current Technologies for ADC, DAC, FPGA, BPM, Kicker,... The development cost ~ 300 k Euro including several processors SPring-8 case in 2004, we paid Tokyo Electron Device 20 M JPY ( 150 k Euro at the rate in 2004 ) 3 Processors for 500MHz, FPGA program, Linux device driver / Application for USB control Half year after specification was fixed Acknowledgement: K. Kobayashi (SPring-8) for development of SPring-8 feedback Tokyo Electron Device Limited (http://www.teldevice.co.jp/eng/index.html) for the help at the development of SPring-8 feedback and discussion on performance of current FPGA Multi-bunch Feedback For 2GHz Bunch rate ?

42. Lower Noise More Number of Bits If are Required How about Square Wave Mixing Front-End

43. Lower Noise, More Bits => Square Wave Mixing Front-End Lower Noise More Number of Bits 16-bit ADC ( AD 9467-250 ) Slow Sampling Rate< 250 MHz Low Input Frequency 70dB If are Required SNR 73 dB 300MHz0MHz AD 9467-250 (16bit, 250MS/s) Square Wave Mixing (24-way) Sampling Rate : 2 GS/s => 167 MS/s Bandwidth: 1 GHz=> 150 MHz Big margin for Sampling Jitter! SNR Low jitter Frequency divider f B => f B /12 is required (or Frequency Multiplier f B /12 => f B ) 75 dB

44. Square Wave Mixing : 6-way (500MHz/2 -> 117 MHz) 85 MHz =500/6. 1ns 2ns 117MHz 6ns ADC 500MHz, 6-way 250 MHz => 117MHz 85 MS/s Signal Divider 2GHz, 24-way 1GHz => ~ 117MHz, 167MS/s T. Nakamura, et al. http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf Contamination from Neighboring bunches ADC sampling Frequency Response by contamination Low Jitter !!

45. Simultaneous suppression of 10mA/bunch mode-coupling instability + 0.05mA/bunch train multi-bunch Instability By Bunch Current Sensitive Automatic Attenuator EPAC’08, Genoa ICALEPCS’09, Kobe

46. High Resolution BPM Bunch Current x Position Bunch Current Singlet 10 mA 0.05mA/bunch High Efficiency Kicker Bunch train Bunch Current Sensitive Automatic Attenuator Digital Control Analog Control ADC Signal Divider Position DAC FPGA Bunch Current => Attenuation AB A+B A-B Storage Ring Kick Signal 508MS /s FPGA 12-bit ADC 12-bit ADC 12-bit ADC 12-bit ADC Signal Divider Digital Signal Processing ( FIR filter ) SPring-8 Feedback Processor DAC ( Fast Variable Attenuator ) 1/Bunch Current Digital Bunch-by-bunch Feedback System