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ECE2030 Introduction to Computer Engineering Lecture 20: Datapath and Microcode Control Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.

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Presentation on theme: "ECE2030 Introduction to Computer Engineering Lecture 20: Datapath and Microcode Control Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering."— Presentation transcript:

1 ECE2030 Introduction to Computer Engineering Lecture 20: Datapath and Microcode Control Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2 2 2 ISA Implementation Putting everything together A Datapath Unit –Register File  A Collection of Registers –Operation Control Decoding Instruction Generating Control Signals to Orchestrate Hardware –Functional Units Arithmetic Units Logical Units Memory Units

3 3 3 Register File (32 32-bit Registers) 32-bit register R0 031 Data In Data Out 32-bit register R1 32-bit register R2 32-bit register R31 32-bit register R30 read 0 1 2 31 w w w w w 30 Reg encoding 0 1 2 31 30 Reg encoding En WriteRead

4 4 4 Register File with Multiple Ports Xra: X read address Yra: Y read address Xdo: X data out Ydo: Y data out Zwa: Z write address Zdi: Z data in we: write enable This register file has –2 read ports –1 write port –32 registers, each 32-bit XraYraZwa Ydo XdoZdi 32 555 RegFile Clock we

5 5 5 Adder/Subtractor Unit 32 Carry in 32 Carry out En ā/s 0: add 1: subtract F Flags Overflow Zero flag A B AU

6 6 6 Logical Unit 32 En LF F A B 4 ABF0F0 F1F1 F2F2 F3F3 F4F4 F5F5 F6F6 F7F7 F8F8 F9F9 F 10 F 11 F 12 F 13 F 14 F 15 000000000011111111 010000111100001111 100011001100110011 110101010101010101 A·B ABAB A+B A B Ā  B ABAB A·B LU

7 7 7 Logical Unit Bit Slice Implementation LF0 LF1 LF2 LF3 AnBn An·Bn 4-to-1 Mux 0 0 0 1 1 0 0 1 LF0 LF1 LF2 LF3 AnBn 4-to-1 Mux An  Bn

8 8 8 Logical Unit Bit Slice Alternative LF0 LF1 LF2 LF3 0 1 6 15 An Bn Fn 4-to-16 Decoder

9 9 9 Shift Unit B = shift amount Shift Type (ST) –00 = no shift –01 = logical shift –10 = arithmetic shift –11 = rotate Shift Direction (SD) –0 = left –1 = right 32 En ST F A B 2 SD SU

10 10 Combined with Register File XraYraZwa Ydo XdoZdi 555 32 RegFile Clock we 32 Cin 32 Cout En ā/s Flags A B 32 Datapath AU

11 11 Single Cycle Datapath XraYraZwa Ydo XdoZdi 555 32 RegFile Clock we Cin 32 Cout En ā/s Flags AB 32 AU LF AB LU ST AB SU SD

12 12 Arithmetic and Logic Unit (ALU) 32 ā/s A B ALU LF ST SD ALS 00: AU 01: LU 10: SU 11: disable ALU 4 2 2 I omit some input/output e.g. carry, flags etc. Cin Cout En ā/s Flags AB AU LF AB LU ST AB SU SD

13 13 Single Cycle DataPath XraYraZwa Ydo XdoZdi 555 32 RegFile Clock we 32 A B ALU ā/s LF ST SD 4 2 ALS 2

14 14 32 DataPath with Immediate Input XraYraZwa Ydo XdoZdi 555 32 RegFile Clock we 32 A B ALU ā/s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 0 Immediate Enable

15 15 DataPath with Memory 32 XraYraZwa Ydo Xdo Zdi 555 32 RegFile Clock we 32 AB ALU ā/s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 0 Memory Address Data msel r/w ld enable load $Z, ($X) st enable store $Y, ($X)

16 16 Instruction Execution Instruction Fetch –Given a PC address –Retrieve instruction from memory (or cache) Instruction Decode –Instruction type, operands, etc. –Control signals Instruction Execute –Functional unit binding Instruction Complete –Writeback to register or memory Can be done in single cycle or multiple cycles –Instruction complexity (CISC vs. RISC) –Pipelining

17 17 Microcode Sequencer For a multi-cycle implementation or a CISCy ISA –Think about an x86 “ string copy ” instruction An ISA instruction is translated into several microinstructions or microcode These microinstructions –One per cycle –Harness the detailed signals inside a processor –Define low-level control signals in a given state Microcode Sequencer –A finite state machine –Generate microinstruction sequence Most of RISC instructions is one-to-one mapping Could be implemented as a ROM or a PLA

18 18 Microcode Memory Datapath Control Signals State register Needed for a multi-cycle instruction implementation Microcode Memory (ROM or PLA) Combinational Logic Instruction Register

19 19 Microcode Memory Datapath Control Signals Microcode Memory (ROM or PLA) Combinational Logic Instruction Register Our Single-Cycle Microcode Memory  Assume all steps finish within one cycle  No state needed  Not really a microcode sequencer

20 20 A Simple Processor X 5 Y 5 Z 5 imm 16 imm_en we ALS 2 ā/s LF 4 ST 2 SD ld_en st_en ṝ/w msel Instruction Register Microcode Memory (Single-Cycle Implementation) Memory 32 Program Counter 32 Next PC gen Single Cycle Datapath

21 21 A Simple Processor X=00011 Y=00010 Z=00100 imm=0 imm_en=0 we=1 ALS=00 ā/s=0 LF=0000 ST=00 SD=0 ld_en=0 st_en=0 ṝ/w=0 msel=0 Microcode Memory Single Cycle Datapath 00000001100010001000000010000000 31 opcode rs rtrd 26252120161511106 50 shamtfunct add $4, $3, $2 add $4, $3, $2

22 22 Datapath Control Signals 32 XraYraZwa Ydo Xdo Zdi 555 32 RegFile Clock we 32 AB ALU ā/s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 0 Memory Address Data msel r/w ld enable st enable imm enable 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag 0001: AND 0011: A 0101: B 0110: XOR 0111: OR

23 23 Microcode Control (1) Clear memory location 100, 104 (r0 hardwired to 0)  instruction sequence X (5)Y (5)Z (5)wewe Imm_enImm_valALSā/sLFSTSDld_enst_en ṝ /w msel li r1,100 sw r0, (r1) addi r1,r1,4 sw r0, (r1) ALS 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag (LF) 0001: AND 0011: A 0101: B 0110: XOR 0111: OR Datapath Control Signals

24 24 Microcode Control (1) Clear memory location 100, 104 (r0 hardwired to 0)  instruction sequence X (5)Y (5)Z (5)wewe Imm_enImm_valALSā/sLFSTSDld_enst_en ṝ /w msel li r1,100 xx00001110x006401x0101xx00x0 sw r0, (r1) 0000100000x00x11xxxx0111 addi r1,r1,4 00001x 110x0004000xxx00X0 sw r0, (r1) 0000100000x00x11xxxx0111 ALS 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag (LF) 0001: AND 0011: A 0101: B 0110: XOR 0111: OR

25 25 Microcode Control (2) copy 4-byte data from 0xF000 to 0xA100 clear data at 0xF000  instruction sequence X (5)Y (5)Z (5)wewe Imm_enImm_valALSā/sLFSTSDld_enst_en ṝ /w msel li r5, 0xF000 lw r6, (r5) li r7, 0xA100 sw r6, (r7) sw r0, (r5) ALS 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag (LF) 0001: AND 0011: A 0101: B 0110: XOR 0111: OR

26 26 Microcode Control (2) copy 4-byte data from 0xF000 to 0xA100 clear data at 0xF000  instruction sequence X (5)Y (5)Z (5)wewe Imm_enImm_valALSā/sLFSTSDld_enst_en ṝ /w msel li r5, 0xF000 XX00101110xF00001X0101XX00X0 lw r6, (r5) 00101X0011010X11XXXX1001 li r7, 0xA100 XX00111110xA10001X0101XX00X0 sw r6, (r7) 0011100110X00X11XXXX0111 sw r0, (r5) 0010100000X00X11XXXX0111 ALS 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag (LF) 0001: AND 0011: A 0101: B 0110: XOR 0111: OR

27 27 Microcode Control (3) Perform r2 = 5  *(r2 – 2*r3) + 3*r4 store r2 to location stored in r10  instruction sequence X (5)Y (5)Z (5)wewe Imm_enImm_valALSā/sLFSTSDld_enst_en ṝ /w msel sll r3, r3, 1 sub r2, r2, r3 sll r5, r2, 2 add r2, r5, r2 sll r6, r4, 1 add r4, r6, r4 add r2, r2, r4 sw r2, (r10) ALS 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag (LF) 0001: AND 0011: A 0101: B 0110: XOR 0111: OR

28 28 Microcode Control (3) Perform r2 = 5  *(r2 – 2*r3) + 3*r4 store r2 to location stored in r10  instruction sequence X (5)Y (5)Z (5)wewe Imm_enImm_valALSā/sLFSTSDld_enst_en ṝ /w msel sll r3, r3, 1 00011X 110x000110XX01000X0 sub r2, r2, r3 00010000110001010X001XXX00X0 sll r5, r2, 2 00010X00101110x000210XX01000X0 add r2, r5, r2 0010100010 10X000XXX00X0 sll r6, r4, 1 00100X00110110x000110XX01000X0 add r4, r6, r4 0011000100 10X000XXX00X0 add r2, r2, r4 00010001000001010X000XXX00X0 sw r2, (r10) 0101000010X00X11XXXX0111 ALS 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag (LF) 0001: AND 0011: A 0101: B 0110: XOR 0111: OR

29 29 Instruction Fetching (PC Update) Program Counter 32 Memory Instruction Register 32 Microcode ROMDatapath 32x32 RegFile Next PC generation addr data

30 30 Sequential Instruction Fetch Program Counter 32 + 4 Instruction Register 32 Microcode ROMDatapath 32x32 RegFile Memory addr data

31 31 Branch Support Program Counter 32 + 4 beq bne (if true) ext 0 1 mux Instruction Register 32 Microcode ROMDatapath 32x32 RegFile Memory addr data Offset (from  ROM)

32 32 Branch and Jump Support Program Counter 32 + 4 beq bne (if true) ext Offset (from  ROM) 0 1 0 1 mux 0 1 ext Target addr (from  ROM) jr j jr/j Instruction Register 32 Microcode ROMDatapath 32x32 RegFile rs Memory addr data

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