1. Truth Table and Fault Matrix By Dr. Amin Danial Asham

2. References An Introduction to Logic Circuit Testing

3. TEST GENERATION FOR COMBINATIONAL LOGIC CIRCUITS

4. Fortunately, a complete truth table exercise of the logic circuit is not necessary−only the input combinations that detect most of the faults in the circuit are required. The efficiency of a test set is measured by a figure of merit called fault coverage. The term fault coverage refers to the percentage of the possible single stuck- at faults that a test set will detect. TEST GENER ATION FOR COMBINATIONAL LOGIC CIRCUITS (continue)

5. TEST GENER ATION FOR COMBINATIONAL LOGIC CIRCUITS Several distinct test generation methods have been developed over the years for combinational circuits. These methods are based on the assumptions that a.a circuit is non redundant and b.only a single stuck-at fault is present at any time.

7. Example 1: let us consider the circuit shown in and assume that tests for faults α s-a-0 and β s-a-1 have to be derived. Fault Matrix

8. Example 2: Fault Matrix Essential Tests Equivalent Tests An essential test is the one that detects a fault no other tests can detect. An essential test is corresponding to a single 1 in in the fault matrix. Equivalent tests: each test detects the same faults as the others

9. Example 2 (continue) Minimal Test Set

10. Solved Examples

11. Example:1 ABCff1 f s-a-0 f2 d s-a-1 00000000 00100101 01000000 01110110 10000000 10110110 11000000 11110110 d f Drive the tests for faults f s-a-0 and d s-a-1 using fault matrix. ABCf s-a-0d s-a-1 0011 0111 Minimal Test Set Essential Equivalent

12. d e f Example:2 Drive the tests for faults d s-a-0, e s-a-0, and f s-a-0 using fault matrix. ABCff1 d s-a-0 f2 e s-a-0 f3 f s-a-0 0001110001 0011110001 0101110001 0110110110 1001110001 1011110001 1101110001 1111110001 ABCd s-a-0e s-a-0f s-a-0 01111 0001

13. Thanks