1. Exceptions and Interrupts Chap 7, 8 Tae-min Hwang

2. Index 1 Overview 2 Exception management 3 Exception processing 4 Interrupt latency and exception handling optimization

3. Overview 1. The peripheral asserts an interrupt request to the processor 2. The processor suspends the currently executing task 3. The processor executes an Interrupt Service Routine (ISR) to service the peripheral, and optionally clear the interrupt request by software if needed 4. The processor resumes the previously suspended task Typical Interrupt sequence

4. Overview Number 1 ~ 15 for system exceptions Number 16 ~ for interrupt inputs The exception number is used as the identification for each exception and is used in various places in the ARMv7-M architecture Exception types

5. Overview Interrupt number(e.g., Interrupt #0) refers to the interrupt inputs to the NVIC on the Cortex-M processor for efficiency in some of API functions(e.g., when setting up priority levels) System exceptions use negative values Note

6. Exception management There are a number of programmable registers for managing interrupts and exceptions(e.g. NVIC, SCB) Special registers inside the processor core for interrupt masking(e.g. PRIMASK, FAULTMASK, BASEPRI) NVIC and SCB located in SCS address range from 0xE000E000, with size of 4KB (equal to SysTick timer, MPU, debugger register, etc.) Only be accessed by code running in privileged access level except Software Trigger Interrupt Register(STIR) For general application programming, the best practice is to use the CMSIS-Core access functions It is possible to directly access registers in NVIC or SCB if needed, but not recommended because of software portability when porting code from one Cortex-M processor to another with a different processor type Overview

7. There are a number of registers in the NVIC for interrupt control (exception type 16 up to 255) By default, after a system reset: All interrupts are disabled (enable bit = 0) All interrupts have priority level of 0 (highest programmable level) All interrupt pending statuses are cleared The CMSIS-Core provides the following functions for accessing Interrupt Enable registers: void NVIC_EnableIRQ (IRQn_Type IRQn); // Enable an interrupt void NVIC_DisableIRQ (IRQn_Type IRQn); // Disable an interrupt NVIC registers Exception management

8. These registers are related to interrupts or exception control The ICSR register can be used by application code to: - Set and clear the pending status of system exceptions including SysTick, PendSV, and NMI. -Determine the currently executing exception/interrupt number by reading VECTACTIVE SCB registers

9. Exception management All of these registers are special registers PRIMASK is used for temporarily disable all interrupts to carry out some timing critical tasks void __enable_irq(); // Clear PRIMASK void __disable_irq(); // Set PRIMASK void __set_PRIMASK(uint32_t priMask); // Set PRIMASK to value uint32_t __get_PRIMASK(void); // Read the PRIMASK value BASEPRI used for want to disable interrupts with priority lower than a certain level FAULTMASK used for wand to disable interrupts with priority lower than a certain level It is very similar to PRIMASK except that it changes the effective current priority level to -1, so that even the HardFault handler is blocked, so Only the NMI exception handler can be executed when FAULTMASK is set void __enable_fault_irq(void); // Clear FAULTMASK void __disable_fault_irq(void); // Set FAULTMASK to disable interrupts void __set_FAULTMASK(uint32_t faultMask); uint32_t __get_FAULTMASK(void); PRIMASK, FAULTMASK, BASEPRI

10. Exception management Some of the exceptions (e.g. reset, NMI, and HardFault) have fixed priority levels M3 and M4 supports up to 256 levels of programmable priority(with a maximum of 128 levels of pre-emption, and most Cortex-M3 or Cortex-M4 chips have fewer supported levels - for example, 8, 16, 32, and so on) Reduction in levels is implemented by cutting out the least significant bit (LSB) part of the priority configuration registers Controlled by priority-level registers, with width of 3bits to 8 bits For general application programming, the best practice is to use the CMSIS-Core access function Definitions of priority Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0 ImplementedNot Implemented A priority-level register with 3 bits implemented (8 programmable priority levels) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0 ImplementedNot Implemented A priority-level register with 4 bits implemented (16 programmable priority levels)

11. Exception management #IRQ1 has higher priority level In default(4-bit priority configuration) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0 ImplementedNot Implemented #IRQ00x09 #IRQ10x03 1010 0000 0101 1111 If LSB removed #IRQ00x04 #IRQ10x01 1010 0000 0101 1111 #IRQ1 has higher priority level # IRQ0 has higher priority level #IRQ00x01 #IRQ10x03 1010 0000 0101 1111 If MSB removed

12. Exception management Using a configuration register in the System Control Block (SCB) called Priority, the priority-level configuration registers for each exception with programmable priority levels is divided into two halves, the group (pre-empt) priority and the lower half (right bits) is the sub-priority The group priority level defines whether an interrupt can take place when the processor is already running another interrupt handler. The sub-priority level value is used only when two exceptions with same group-priority level occur at the same time. In this case, the exception with higher sub-priority (lower value) will be handled first Priority Groups NVIC_DecodePriority are returned by modified values pointed by the pointers uint32_t *pPre emptPriority uint32_t *pSub priority Note

13. Exception management There are a number of programmable registers for managing interrupts and exceptions(e.g. NVIC, SCB) Special registers inside the processor core for interrupt masking(e.g. PRIMASK, FAULTMASK, BASEPRI) NVIC and SCB located Priority Groups 0(default) 1 2 3 4 5 6 7 Bit [7:1] Bit [7:2] Bit [7:3] Bit [7:4] Bit [7:5] Bit [7:6] Bit [7:7] None Bit [0] Bit [1:0] Bit [2:0] Bit [3:0] Bit [4:0] Bit [5:0] Bit [6:0] Bit [7:0] Priority GroupsPre-empts Priority FieldSub-priority Field

14. Exception management 3-bit priority-level register with priority group set to 5 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0 Preempt priority Not Implemented Sub- priority 5Bit [7:6]Bit [5:0] Priority GroupsPre-empts Priority FieldSub-priority Field 3-bit priority-level register with priority group set to 1 Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0 Preempt priority[5:3]Sub-priority[1:0]Preempt priority[2:0] 1Bit [7:2]Bit [1:0] Priority GroupsPre-empts Priority FieldSub-priority Field Always 0

15. Exception management Cortex -M processor accepts an exception request, the processor needs to determine the starting address of the exception handler, and this information is stored in the vector table in the memory The vector table is normally defined in the startup codes provided by the microcontroller vendors Vector table Because of possibility that some exception such as NMI could happen as the processor just came out from reset and before any other initialization steps are executed

16. Exception management The vector tables in the Cortex-M processors are different from the vector tables in traditional ARM processors Vector table relocation Note Traditional ARM processors : Contain instructions such as branch instructions to branch to appropriate handlers Cortex-M processors : Contain the starting addresses of exception handlers It is useful to be able to modify or define exception vectors at run-time, so the Cortex-M3 and Cortex-M4 processors support a feature called Vector Table Relocation Vector Table Relocation feature provides a programmable register called the Vector Table Offset Register (VTOR) The VTOR register has a reset value of zero, and in application programming with a CMSIS-compliant device driver, this register can be accessed as “SCB->VTOR.” This register defines the starting address of the memory being used as the vector table Note VTOR register is slightly different between Cortex-M3 revision r2p0 and revision r2p1 Cortex-M3 r2p0 : the vector table can only be in the CODE region or the SRAM region Cortex-M3 r2p1 and Cortex-M4: The restriction is removed

17. Exception management Vector table reallocation Bit 31:30Bit 29Bit 28:7Bit 6:0 TBLOFFReserved TBLBASETBLOFFReserved Vector Table Offset Register(VTOR), address 0xE000ED08 TBLOFF : Vector Table Base Offset TBLBASE : Table based in CODE(0) region or SRAM(1) region Reserved : Read as zero, write ignore Cortex-M4 or Cortex-M3 r2p1 Cortex-M3 r0p0 to r2p0 Example code (beginning of SRAM 0x20000000) #define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS))) #define VTOR_NEW_ADDR 0x20000000 int i; for(i=0;i<48;i++){// Copy original vector table to SRAM first before programming VTOR HW32_REG((VTOR_NEW_ADDR + (i<<2))) = HW32_REG((i<<2)); // Assume maximum number of exception is 48 } __DMB(); // Data Memory Barrier to ensure write to memory is completed SCB->VTOR = VTOR_NEW_ADDR; // Set VTOR to the new vector table location __DSB(); // Data Synchronization Barrier to ensure all subsequence instructions use the new configuration

18. Exception management There are various status attributes applicable to each interrupt : - Each interrupt can either be disabled (default) or enabled - Each interrupt can either be pending (a request is waiting to be served) or not pending - Each interrupt can either be in an active (being served) or inactive state To support this, the NVIC contains programmable registers for interrupt enable control, pending status, and read-only active status An interrupt request can be accepted if ① The pending status is set, ② The interrupt is enabled, ③ The priority of the interrupt is higher than the current level(including interrupt masking register configuration) The NVIC is designed to support peripherals that generate pulsed interrupt requests as well as peripherals with high level interrupt request (the pulse must be at least one clock cycle long, and no need to configure any NVIC register to select either interrupt type) For level triggered interrupts, the peripheral requesting service asserts the request signal until it is cleared by an operation inside the ISR The request signals received by the NVIC are active high, although the external interrupt request at the I/O pin level could be active low Interrupt inputs The interrupt request

19. Exception processing It means it is put into a state of waiting for the processor to serve the interrupt If the processor is already serving another interrupt of higher or equal priority, or if the interrupt is masked by one of the interrupt masking registers, the pended request will remain until the other interrupt handler is finished, or when the interrupt masking is cleared In traditional ARM processors, the devices must be hold the request until they are served Pending behaviors

20. Exception processing Pending behaviors Cases Interrupt Request Interrupt Pending status Processor mode Pending status cleared by software Interrupt pending status cleared before processor serving the interrupt Interrupt Request Interrupt Pending status Processor mode Pending status cleared by software and re-asserted Cleared before re-asserted due to continuous interrupt request Thread mode Interrupt return Interrupt re-entered Interrupt Request Interrupt Pending status Processor mode Interrupt get its pending status set again if the request is still asserted after exception exit Processor mode Thread mode Handler mode Multiple interrupt pulses before entering ISR Interrupt Request Interrupt Pending status Processor mode Interrupt get its pending Processor mode Thread mode Handler mode

21. Exception processing The processor accepts an exception if the following conditions are met - The processor is running (not halted or in reset state) -The exception is enabled (with special cases for NMI and HardFault exceptions, which are always enabled) -The exception has higher priority than the current priority level -The exception is not blocked by an exception masking register (e.g., PRIMASK) If the SVC instruction is accidentally used in an exception handler that has the same or higher priority than the SVC exception itself, it will cause the HardFault exception handler to execute An exception entrance sequence contains several operations : -Stacking of a number of registers, including return address to the currently selected stack. This enables an exception handler to be written as a normal C function -Fetching the exception vector (starting address of the exception handler/ISR) -Fetching the instructions for the exception handler to be executed -Update of various NVIC registers and core registers Within the exception handler, you can carry out services for the peripheral that requires service. The processor is in Handler mode when executing an exception handler In ARM Cortex -M processors, the exception return mechanism is triggered using a special return address called EXC_RETURN Exception sequence

22. Exception processing As the processor enters the exception handler or Interrupt Service Routine (ISR), the value of the Link Register (LR) is updated to a code called EXC_RETURN The value of this code is used to trigger the exception return mechanism when it is loaded into the Program Counter (PC) using BX, POP, or memory load instructions (LDR or LDM) Some bits of the EXC_RETURN code are used to provide additional information about the exception sequence EXC_RETURN

23. Exception processing C compilers for ARM architecture follow a specification from ARM called the AAPCS According to AAPCS, a C function can modify R0 to R3, R12, R14 (LR), and PSR R0-R3, R12, LR, and PSR(+ S0-S15 in Cortex-M4) are called “caller saved registers” R4-R11(+ S16-S31 in Cortex-M4) are called “callee-saved registers” Typically, a function call uses R0 to R3 as input parameters, and R0 as the return result, and if the return value is 64 bits, R1 will also be used as the return result Exception Handler in C The block of data that are pushed to the stack memory at exception entrance Stack frame

24. Exception processing When an exception occurs and is accepted by the processor, the stacking sequence starts to push the registers into the stack, forming the stack frame In parallel to the stacking operation (usually on the System bus), the processor can also start the vector fetch(Because of Havard architecture) Exception entrance and stacking At the end of an exception handler, the bit 2 of the EXC_RETURN value generated at the exception entrance is used to decide which stack pointer should be used to extract the stack frame If bit 2 is 0, the processor knows that the main stack was used for stacking To reduce the time required for the unstacking operation, the return address (stacked PC) value is accessed first, so that instruction fetch can start in parallel with the rest of the unstacking operation) Exception return and unstacking

25. Interrupt latency and exception handling optimization The term interrupt latency refers to the delay from the start of the interrupt request to In the Cortex-M3 and Cortex-M4, if the memory system has zero latency, and provided that the bus system design allows vector fetch and stacking to happen at the same time, the interrupt latency is only 12 clock Some situations can increase the interrupt latency -The processor was serving another exception at the same or higher priority. -Debugger accesses to the memory system. -The processor was carrying out an unaligned transfer. From the processor point of view, this might be a single access, but at the bus level it takes multiple cycles, as the bus interface needs to convert the unaligned transfer into multiple aligned transfers. -The processor was carrying out a write to bit-band alias. The internal bus system converts this into a read-modify-write sequence, which takes at least two cycles Interrupt latency When an exception takes place but the processor is handling another exception of the same or higher priority, the exception will enter the pending state the processor skips the unstacking and stacking steps and enters the exception handler of the pended exception as soon as possible Tail Chaining

26. Interrupt latency and exception handling optimization During stacking operation another exception of higher priority takes place, the higher priority late arrival exception will be serviced first Late arrival If an exception request arrives during the unstacking process of another exception handler that has just finished, the unstacking operation would be abandoned and the vector fetch and instruction fetch for the next exception service begins Pop preemption