1. Memory Access Instructions Load and Store Addressing Modes Memory Addressing. Base addressing mode. Load byte and store byte: lb, lbu, sb Address alignment. Big Endian, Little Endian. Load word. Store word. Load halfword. Store halfword. lw, sw, lh, lhu, sh Setting Up the base register Low order result. Portability problems Textbook: Chapter 3. Appendix A Central Connecticut State University, MIPS Tutorial. Chapters 15,16.

2. Review: MIPS model 2 32 cells, each 8 bits 2 32 bytes Memory Size Address 32 bits MIPS memory is an array of 2 32 bytes. Each byte has a 32-bit address. Each byte can hold an 8-bit pattern, one of the 256 possible 8-bit patterns. The addresses of MIPS main memory range from 0x00000000 to 0xFFFFFFFF. Operations Load: a bit pattern starting at a designated address in memory is copied into a register inside the processor. Store: a bit pattern is copied from a processor register to memory at a designated address. General Purpose Register

3. Byte operations 2 32 bytes Memory Size Address 32 bits General Purpose Register Load byte Memory byte -> Register byte Store byte Register byte -> Memory byte 3 2 1 0 Low order

4. 2 32 bytes Memory Size Address 32 bits General Purpose Register 3 2 1 0 Halfword operations Load halfword Memory 2 bytes -> Register 2 bytes Store halfword Register 2 bytes -> Memory 2 bytes Load halfword Memory 2 bytes -> Register 2 bytes Store halfword Register 2 bytes -> Memory 2 bytes Low order

5. 2 32 bytes Memory Size Address 32 bits General Purpose Register 3 2 1 0 Word length operations Load word Memory 4 bytes -> Register 4 bytes Store word Register 4 bytes -> Memory 4 bytes Load word Memory 4 bytes -> Register 4 bytes Store word Register 4 bytes -> Memory 4 bytes Low order

6.  Addressing mode – One of several addressing regimes delimited by their varied use of operands and or addresses.  The first two modes we have learned. Addressing Modes 1. Immediate addressing, where the operand is a constant within the instruction itself 2. Register addressing, where the operand is a register 3. Base or displacement addressing, where the operand is at the memory location, whose address is the sum of a register and a constant in the instruction

7.  A MIPS instruction is 32 bits (always).  A MIPS memory address is 32 bits (always).  How can a load or store instruction specify an address that is the same size as itself ? Memory Instructions need Address & Register  To transfer a word of data, we need to specify two things:  Register: We specify this by # ($0 - $31) or symbolic name ($s0,…,$t0,…)  Memory address: This is more difficult to specify.

8.  Memory is a single one-dimensional array, so we can address it simply by supplying a pointer to a memory address.  However very often, we want to be able to offset from this pointer.  This is because sometimes we need only the relative address to refer to the memory starting from some current address.  That relative address is called “offset”. Offset and absolute address complicate our task Absolute pointer 0x00000006 Relative pointer(offset) +2 Relative pointer(offset) -3 +2 -3

9. So for memory addressing we need:  Either the absolute 32 bit address of the memory  Or The offset (relative address) of the memory  In this case to calculate the absolute address of the memory we need the offset and some current or base absolute address. Base address + Offset Base Address = 0x00000006 Calculated address = 0x00000006+2=0x00000008 Calculated address = 0x00000006-3=0x00000003 +2 -3

10. Where to keep the Base Address and Offset ? To specify a memory address specify two things: A register containing a base 32 bits address to memory A numerical offset in bytes in the instruction The desired memory address is the sum of these two values. Example: 8($t0) specifies the memory address pointed to by the value in $t0, plus 8 bytes

11. What looks like the memory access instruction ? Why sign extension ? lb rt, MemAaddress lb rt, offset (rs) offset

12. Addressing examples positive offset

13. Addressing examples negative offset