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Busses. Peripheral Component Interconnect (PCI) bus architecture The PCI bus architecture is a processor-independent bus specification that allows peripherals.

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Presentation on theme: "Busses. Peripheral Component Interconnect (PCI) bus architecture The PCI bus architecture is a processor-independent bus specification that allows peripherals."— Presentation transcript:

1 Busses

2 Peripheral Component Interconnect (PCI) bus architecture The PCI bus architecture is a processor-independent bus specification that allows peripherals to access system memory directly without using the CPU. This frees up the CPU to service other application calls. The PCI bus replaced the earlier Industry Standard Architecture (ISA) bus.

3 PCI Bandwidth NameMaximum Bandwidth (MB/s) ISA 8-bit7.9 ISA 16-bit15.9 PCI132 AGP 8X2100 PCI Express 1x250 [500] PCI Express 2x500 [1000] PCI Express 4x1000 [2000] PCI Express 8x2000 [4000] PCI Express 16x4000 [8000] PCI Express 32x8000 [16000]

4 Other Busses NameMaximum Bandwidth USB 2.0480 Mbps half duplex USB 3.04.9 Gbps full duplex SATA I1.5 GB/s SATA II3.0 GB/s SATA III6.0 GB/s IDE (ATA 100) aka PATA 100100 MB/s IDE (ATA 133) aka PATA 133133 MB/s Serial Port115 KB/s Gigabit Ethernet125 MB/s IEEE 1394B [Firewire 800]~100 MB/s

5 Acronyms AGP = Accelerated Graphics Port ATA = Advanced Technology Attachment IDE = Integrated Device Electronics PATA = Parallel ATA PCI = Peripheral Component Interconnect PCIe/PCIE = Peripheral Component Interconnect Express SATA = Serial ATA USB = Universal Serial Bus

6 Acronyms CPU = Central Processing Unit GPU = Graphics Processing Unit APU = Accelerated Processing Unit AMD’s CPU + Radeon GPU on a single chip


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