1. 1 Memristive Computing Sangho Shin sshin@soe.ucsc.edu Dept. of EE, UCSC January 29 th, 2013 Winter 2013 EE222-lecture7

2. 2 Outlines Background: Memristive Computing – Definitions – Technical Area and Research Opportunities – Memristors and Memristive Devices Past and Current Trends – Memristive Storage Systems – Memristive Logic and Computing Systems Looking into Future

3. 3 ‘Memristive Computing’ What is ‘Memristive Computing’? – Any set of circuits which utilizes ‘memristive’ electronic properties in computing/processing information. May or may not include actual ‘memristor’ or ‘memristive device’. – Which behaviors are ‘Memristive’? Utilizations of ‘dynamic nonvolatile resistance’ as the fundamental state variable for data storage/computing/etc. – Alternate term is ‘Resistive Computing’.

4. 4 ‘Memristive Computing’ Focal Areas of Related Research – Resistive memory system that stores information in its ‘resistance’ Resistive Random Access Memory (RRAM), Phase-Change RAM (PCRAM), Magnetic RAM (MRAM), etc. Nonvolatile-VLSI/SRAM/analog/etc. – Stateful logic: computes/registers Boolean functions/states Stateful NAND, AND, NOR, OR, XOR, XNOR, etc. Memristive logic array, pattern matcher/searcher – Reconfigurable electronics Memristors-based threshold logic, memristive FPGA, programmable stateful logic array, adaptable electronics, etc. – Learning/interconnecting machine that utilizes memristance Memristive synaptic network, neuromorphic computing, etc.

5. 5 Memristors and Memristive Devices Distinctive Capabilities of Memristors – Defines the missing link btwn. charge (q) and flux-linkage (  ) – Capabilities both for “Resistor” and “Memory” – “Conditional” SET or RESET, depending on the applied voltage Enables “logic” functions in the memristor devices Potential Applications of Memristive Devices – Analog/binary/multi-level nonvolatile memory – Analog/digital signal processing – Reconfigurable systems – Logic elements “Conditional” SET and RESET Memristor as 4 th fundamental device

6. 6 Memristive Devices and Systems Examples –Hodgkin-Huxley Equation, Flourescent Lamp, Thermistor, etc. –Memristor is a special case of memristive systems Current-controlled memristor Voltage-controlled memductor Defined by L. Chua & S.M. Kang in 1976 –A class of nonlinear devices whose resistance is controlled by state variables that incorporate memory effects

7. 7 Nanoscale Memristive Devices Nanotechnology Enabled Memristive Devices – Typically formed in nano crossbar structures Capable of ultra dense integration – Compatible with CMOS process Enables hybrid CMOS/Nanodevices integration

8. 8 Low-Level Nanowire Crossbar Structure Nanoelectronics Devices –At each cross point of a nanowire crossbar CMOS-nano Interface –PINs on top of CMOS Stack Technical Issues –Addressability of nanodevices –Alignment of CMOS PIN array & nanowire crossbar Nanowires Nanodevices Nanowires Interface PINs Top level wires of CMOS stack oxide

9. 9 CMOS/Nano Hybrid Integration Hybrid 2D/3D Integration – Reconfigurable Nano+CMOS – Extendable to multi-layer addressing/interconnection Ultra-dense Memristive Nanoelectronics – 2D/3D analog/digital memory – Large-scale logic array – Neuromorphic chips – Memristive signal processing

10. 10 Memristor-Embedded CMOS Grand challenge: How can we avoid the complex hybrid technology for CMOS/Nano co-integration? active M3 M4 M1 M2 Nano layer Nanowire crosspoint devices CMOS layer active Interlayer PINs array Memristive-via devices FPNI structureCMOL structureUCSC’s Memristor-embedded CMOS M3 M4 M1 M2

11. 11 Outlines Background: Memristive Computing – Definitions – Technical Area and Research Opportunities – Memristors and Memristive Devices Past and Current Trends – Memristive Storage Systems – Memristive Logic and Computing Systems Looking into Future

12. 12 Memristive Storage Systems Ultra-Dense Persistent Memory – Compatible to hybrid integration with CMOS – Variability-immune storage capability – Fast read/write access – Low-power addressability and readability Search Capability within Memory Systems – Ultra-dense nonvolatile storage for data-intensive applications – Low-latency search for data/text/image/etc. – Energy-efficient storage/search operation – E.g., Content Addressable Memory (CAM) Systems, pattern matchers, etc.

13. 13 Memristive Device as Persistent Memory Key factors of importance – Physical Geometry – Process/Thermal Reliability – Embedding Compatibility into CMOS – 3D Stackability Challenges for Device Technology – Number of Storage Bits/Device – Retention >10 years – Endurance > 10 17 – Read/Write Energy < 1fJ/bit – Read/Write Speed < 1ns

14. 14 RRAM Device Models Functional Model – Captures the threshold sensitive bistable resistance state – Neglecting timing related performance Valid for functional circuit simulations Behavioral Model – With added behaviors of switching transients Valid for behavioral circuit simulations

15. 15 RRAM Device Models Statistical Model – Captures the variability of device parameters – Thresholds, resistance state, and switching speed with statistical distribution Valid for statistical estimation of circuit reliability Behavioral model Statistical model

16. 16 Classes of Nonvolatile RAM Classes of NVRAM – Charge-based memory: EEPROM, FLASH, SRAM – Memristive (resistive) memory: PCRAM, MRAM, RRAM Technology Issues with RRAM – Unreliable device performance (Variability) – Multi-layer memory integration Circuit issues – Speed & Power consumption for read/write operations – Performance degradation by “Sneak currents” – “Data-pattern” sensitive power & read/write performance

17. 17 Issues on Passive Array of RRAMs Technology issues – Unreliable device process (Variability) – Multi-layer memory integration Circuit issues – Power consumption for Write/Read operations – Performance degradation by “Sneak currents” – “Data-pattern” sensitive power & read performance

18. 18 How to deal with “Sneak Currents”? With selection devices (e.g., 1T1R or 1D1R) Trading-off with power ( 0 ≤ v X < v R ) Forced bit-line voltages (e.g., TIA type) Performance(a)(b)(c) Sensing marginLargeNarrowLarge SpeedFast Slow PowerLowModerate ~ HighLow 2D capacityLowHigh 3D stackabilityChallengingGood

19. 19 Sensing Behaviors of RRAMs Passive RRAM with Resistive Terminations – Sensing performance is highly dependent on the stored “Data- pattern”, due to “Sneak Currents” – The more low-resistance cells lead to the lower sensing margin Data-pattern sensitive Read performance (128x128 array)

20. 20 RRAM Modeling Analysis and Estimation of RRAM Performance ( m × n array) – Full node analysis needs to solve for – Computation efficient statistical model for analysis of data- and variability-dependency – Sub-grouping for modeling G I : cell to be read (k, l) G II : cells in reading row G III : cells in reading column G IV : all the others for j =1, 2, …, m

21. 21 2x2 Equivalent Memory Model 2 × 2 equivalent model for n×m RRAM array – Each group is represented in a single equivalent admittance – Capable of flexible analysis and ease of simulation

22. 22 2x2 Model Results Example for 128×128 array – Conditions :  = R OFF /R ON =10 3, ( R OFF =10 M , R ON =10 k  ) – Note: Data-pattern dependent  (= R OFF /R S ) is desirable (a) Detection margin (b) Average cell current Symbols : n×m simulation Lines : 2×2 model

23. 23 Array Size Dependency Optimal R S ( R S.opt ) – R S.opt =~R ON (small array) < R ON (large array) – Sensitive to data-pattern Detection margin (  v S ) – Decreases with array size – Sensitive to data-pattern – For 1% margin, n & m <128

24. 24 Data-Pattern Dependency Highly sensitive performance to data-pattern –  opt /  is approximately linear to data probability – Data dependent optimum  -ratio (  opt = R OFF /R S.opt ) is desirable  -ratio (= R OFF / R ON ) dependency – Generally good for larger  -ratios (rapidly desensitized as  >10 2 )

25. 25 Adaptable R S.opt Example 128×128 RRAM array – R ON =10k , R OFF =10M  (  =10 3 ) – R S constructions by Reconnecting a part of unread RRAM (x=5) Dedicated R OFF rows (y=35)

26. 26 Performance Comparison Worst case vs. self-adaptable design – Self-adaptable design shows the larger  v S and low I cell.av, simultaneously, compared to the worst-case design – Especially for low probability cases Average improvement: + 46% for  v S increment + 14% current reduction

27. 27 Complementary Memory Cell Complementarily written two devices cell (CR-cell) – Provides data-dependent equivalent sense resistance ( R S.eq ) 1R-cell CR-cell Readout circuit configuration Sense resistance Normalized detection margin Normalized average current ><>< < >

28. 28 Array Properties of CR-cell Array Features – Lower design complexity With no optimization process for R S – Data-dependent equivalent R S – Reduced effective density – Doubled number of sneak paths by complementary devices Data-pattern dependency – Constant detection margin With larger window – Regulated readout currents With smaller values 2x2 array of CR-cell memories

29. 29 n xm Dimensional CR-cell Array

30. 30 Write-Mode Configuration 2-Step ‘WORD-wise’ Writing – Step-1: RESET for all devices of a selected word line – Step-2: SET for selected bit devices (other devices are halfway selected) Step-1: RESET Step-2: Selective SET Bit controlled

31. 31 Read-Mode Configuration ‘WORD-wise’ READ – Comparison V S with V REF Reference generation – Desirable to be data- dependent – Finding median V S by dedicated R OFF & R ON columns – Each REF cell has complementary devices (p III =0.5) – Reference buffer isolates capacitances of SAs

32. 32 Variability Effect on Read Performance For a 128x128 array: – Resistances: log-N dist. w/i  =20% – R ON.0 =10k , R OFF.0 =10M  – Array size=128x128 – REF sections for every 8-bits  3  VS.LRS Data-dependent V REF V S.LRS V S.HRS  3  VS.HRS

33. 33 Performance Comparison (I) Array size dependency – Optimally designed 1R-cell array vs. CR-cell array – CR-cell memory is capable of ~4x larger size Symbols : CR-cells array Thin lines: 1R-cells array 1R-cell RRAMCR-cell RRAM Data-pattern independent detection performance

34. 34 Performance Comparison (II) Data-pattern Dependency – Optimally designed 1R-cell array vs. CR-cell array – Lower current consumption for all cases – Data-independent detection performance Symbols : CR-cells array Thin lines: 1R-cells array Voltage Detection Window Sensing Current

35. 35 Ternary CAM Structure Content Addressable Memory (CAM) Architecture – RRAM-based CAMs array (unit array size: nxm) – Capable of storage/search of ternary states – Returns a matched address

36. 36 Ternary CAM Cell NOR-type Content Match – Control bits: Word Select (WS), Search/Write Enables (SE, WE) – Input/Output: Contents Lines (C, C), Match Line (ML) Ternary BITs Read/Search – 2-bit complementary storage – “don’t care” Search with C=C=0

37. 37 CAM Performance Factors Maximum Size of Unit CAM Array – Limited in parts by the Latency & Power specification # of SLs: determined by Latency # of WLs: determined by power consumption – There is no “Sneak” effect Latency participating Components – Input part: ‘Contents driving delay’, ‘V X charging time’ – Evaluation part: ‘ML pre-charging time’, ‘ML pull-down time’ – Output part: ‘SA delay’, ‘Decoding time’ The other delay components will not affect the Latency Power Consumption – Dominated by currents through RRAMs – Total power consumption: ~proportional to # of WLs

38. 38 Reduction of Writing Power

39. 39 Outlines Background: Memristive Computing – Definitions – Technical Area and Research Opportunities – Memristors and Memristive Devices Past and Current Trends – Memristive Storage Systems – Memristive Logic and Computing Systems Looking into Future

40. 40 Computing in Memristive Devices Three distinctive functions of memristive devices – Programmable interconnects – Nonvolatile memory – Conditional SET and RESET of memristance Property of Conditional SET or RESET Enables: – Memristive “logic” and “computing” capable of reconfiguration – High density logics and signal processing through 3D integration e.g., CPU embedded memory – With capability of nonvolatile memory logic functioning + registering – Extends Moore’s Law beyond the CMOS limit

41. 41 Memristive Stateful Logic Gate Stateful NAND Gate via Material Implication Device-Q can be SET “conditionally” depending on the status of P. “Stateful” logic, functioning NAND and registering the output in Q. Implication condition: V EVL < V SET V SET > V CLOSE

42. 42 Reconfigurable logic array architecture – 2D or 3D structured logic array – Multiple fan-in/fan-out Device technology for reliable logic functioning – Distinctive sets of device characteristics regarding accidental interconnection change Design Paradigm Shift – Fine grain pipelined logic architecture Issues for Large Scale Logic Array 1-D array 2-D array

43. 43 Issues: Parallel Execution Pipelined executions to reduce data latency – Simultaneous executions of non-overlapped logics – Overheads: control switches and load resistors Example 3-gates logic

44. 44 Issues: Simultaneous Implications Reduction of data latency – Single 2-input NAND execution requires 3-steps of implications Initialization (CLEAR) + two implication steps (Conditional SET) – High fan-ins seriously increase the data latency – Simultaneous executions of multiple implications are desirable k-input NOR gate with simultaneous implications – Significantly reduces the latency for high fan-ins Fixed-R G Scaled R G-EQ  1/(k+1)

45. 45 Issues: Duplication (I) Explicit duplication requirement for fan-out capability Inversion required for involution! More steps required for large fan-outs! If Q turned ON first, then R cannot be turned ON!

46. 46 Issues: Duplication (II) Solution for simultaneous duplication: AND operation Step-1: SETStep-2: Simultaneous duplication

47. 47 Issues: Mapping to FPNI Fabric (I) NOR operation – Executed during odd numbered schedules – Implication voltages: V CLEAR, V SET, V COND- Mode Step VIVI SISI V II SOSO write 10V CLEAR 0 200 3V COND- 1V SET 0 410 read 1V CLEAR 00 200 3V SET 0V COND- 1 40V COND+ 1 RESET initialization SET initialization NOR operation OR operation & duplication Next pipelined schedule Example of 2-input NOR execution:

48. 48 Issues: Mapping to FPNI Fabric (II) OR & duplication – Executed during even numbered schedules – Implication voltages: V SET, V CLEAR, V COND+ – Dedicated switch (S D ) for duplication control Mode Step VIVI SISI V II SOSO SDSD write 1000 20V SET 00 3100 4V COND+ 1V CLEAR 01 read 1V CLEAR 000 2000 3V SET 0V COND- 10 40V COND+ 10 RESET initialization SET initialization NOR operation OR operation & duplication Next pipelined schedule Example of 2-input 2-output OR execution:

49. 49 Issues: Mapping to FPNI Fabric (III) 2D Stateful NOR Gate and it’s FPNI mapping 2D implementation of k-input NOR gateMapping to FPNI fabric

50. 50 Issues: Implication Voltages Example for k-input NOR gate – Condition: V CLOSE =-1V, V OPEN =1V,  =R OFF /R ON =10 2,  =R OFF /R G =2 – Wide enough triangular solution space of (V SET, V COND- ) Valid voltages space for simultaneous executions of multiple implications Simulation results for k=8,  =8

51. 51 Base Unit for Large-Scale Logic Array

52. 52 Base Unit for Large-Scale Logic Array

53. 53 Capability of Signal Processing

54. 54 Design Paradigm Shift (I) Logic Representation – Staged OR-NOR Graph (SONG)

55. 55 Design Paradigm Shift (II) Hierarchical Assembly: Data Synchronization – Example of 2-bit adder

56. 56 Design Paradigm Shift (III) Hierarchical Assembly: Data Synchronization – Example of hierarchical 4-bit adder 2-bit adder

57. 57 Logic input (x, y ), and output (p) – Steps and Control for Logic Implication – Truth Table for XOR operation Resistive Multiplication: XOR VPVP S1S1 S2S2 Mode Step-IV RST 10 Step-IIV SET 01 Mode 0000 0101 1001 1100

58. 58 Implication Conditions for XOR (V EVL, V SET )= (1, 1.5)xV CLOSE

59. 59 Results of XOR Operation Used Device Parameters: R ON =10k  R OFF =1M  V CLOSE =1V V OPEN =-1V T hold =10ns Circuit Parameters: V SET =1.5V V RST =-1.5V V EVL =1V T STEP =20ns 000 011 101 110

60. 60 Logic input (x, y ), and output (q) – Steps and Control for Logic Implication Resistive Multiplication: XNOR VPVP VQVQ S1S1 S2S2 S3S3 S4S4 Mode Step-IV RST 1001 Step-IIV SET -0100 Step-IIIV EVL V SET 0011 Step-IStep-IIStep-III 00000001 01001010 10001010 11000001

61. 61 Results: XNOR operation Used Device Parameters: R ON =10k  R OFF =1M  V CLOSE =1V V OPEN =-1V T hold =10ns Circuit Parameters: V SET =1.5V V RST =-1.5V V EVL =1V T STEP =20ns 0001 0110 1010 1101

62. 62 Application to Pattern Matcher V xy is proportional to the correlation between the input vector X and the reference vector Y.

63. 63 Results: XOR-Based Pattern Match

64. 64 Matcher Application to Pattern Search

65. 65 Pattern Search Results – Each matcher branch set to store one of the eight binary encoded characters of “ACFILNOR”. – Input character stream of “CALIFORNIA” was fed to the matcher.

66. 66 Memristive Computing: Pros & Cons Enabling Opportunities – Low-power nonvolatile computing (zero standby leakage) – No requirement for dedicated registers (stateful) – Fast computing capability by parallel processing (deep pipeline) – Instant resilience at power shutoff Barriers to Large-Scale Integration – Static power consumption (non-zero active current) – Relatively complex configuration and implication schedule – Sensitivity to the multiple levels of bias voltages – Systems’ lifetime (determined by devices’ reliability ‘Endurance’)

67. 67 Outlines Background: Memristive Computing – Definitions – Technical Area and Research Opportunities – Memristors and Memristive Devices Past and Current Trends – Memristive Storage Systems – Memristive Logic and Computing Systems – Pros and Cons of Memristive Computing Looking into Future

68. 68 Future… Memristive Technology Enabled Nonvolatile Reconfigurable Systems on a Memristive System – That can adapt its own system configuration & application dynamically to environment & requirement