1. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg1 System and DHP Development Module overview Data rates DHP function blocks Module layout Ideas & open questions

2. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg2 Module Layout (modified) DHP chip mounted on sensor module –>90% data reduction need only 1-2 serial links for data out per module side Data handling hybrid could support more than one module

3. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg3 DCD + DHP Signal Processing

4. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg4 Signal Flow and Data Rates DCD: modified ILC design 9x16 cells, x4 output multiplexer

5. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg5 DHP Signal Processing data processing –frame buffer (5-10) –common mode & pedestal correction –0-suppr. –triggered r/o generate DCD & Switcher control signals –clock –slow control

6. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg6 Function Blocks slow control interface: I 2 C … DACs, slow ADC for monitoring temperature etc. clock & timing management (PLL or DLL, delay lines) memory blocks (frames, pedestal) data processing blocks –common mode calculation (& correction) –pedestal correction –(cluster finding) –de-randomizing buffer Gigabit serial transmitter (LVDS, CML…)

7. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg7 Clock Management programmable PLL (or DLL) programmable delay lines LVDS outputs could be implemented as stand-alone chip (i.e. 130nm)

8. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg8 Technologies Vendor (90 nm) min. block size [mm 2 ] price [$] price [€] price/mm 2 [€] bump bond pitch [µm] UMC (Europractice) std. MPW1641.800 2.613 162 ? mini@sic3.57.000 1.991 IBM (MOSIS) std. MPW16100.00062.500 3.906 200  min425.00015.625 3.906 TSMC (Europractice) std. MPW1689.91056.1943.512 180 mini@sic49.8506.1561.539 Chartered (own MPW runs) ??? 130 nm good for analogue performance (i.e. clock management chip DCM), many function blocks and libraries readily available 90 nm better for digital performance and size constraints IBM and Chartered 90nm technologies fully compatible (technology alliance)

9. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg9 DCD wish list I 2 C control interface, programmable slave address (3 bit) x4 output multiplexing (instead of x6) –reduce output frequency from 600 to 400 MHz –outputs 24 (LVDS)  36 (single ended) re-ordered output data format … … single-ended output drivers (CMOS or HSTL …) output pad layout symmetric to DHP input (including power & gnd pads)

10. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg10 DCD wish list Ideas & Suggestions “calculate” common mode in the analogue domain –sum the input signals (join replica currents from all memory cells ) –scale the sum by the number of channels (scaled current mirror) –use additional ADC channel to digitize the common mode one common mode output per DCD –DHP would only need a 6 input adder for cm calculation (instead of a 216 input adder)

11. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg11 use solder bump bonds available with MPW runs 200 µm pitch with 100 µm balls available for IBM (via MOSIS), for UMC and TSMC  check with Europractice (confirmed for 90nm)  no mechanical stress (routing under bump pads possible, only 2 layers!)  ‘no limit’ on the number of bumps per chip  rework of broken chips possible  production yield  need UBM on sensor side (can be done at MPI-HLL?, would be needed anyway for solder mounting of passive components: connector, capacitors)  200µm pitch on DCD inputs (needs different DCD geometry) this almost doubles the chip size! but… DCD wish list Ideas & Suggestions

12. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg12 larger DCD cells  add local memory to store individual offsets per DEPFET pixel  need only 128 word deep memory per cell  possible with given layout area  use low to medium resolution DAC to adjust ADC range by subtracting per pixel offset currents from the input  compensate increased pedestal current dispersion after radiation or even better:  store individual pedestal currents and subtract from input with high resolution DAC for faster read-out sequence (‘sample-clear’ instead of ‘sample-clear-sample’)  reduce occupancy DCD wish list Ideas & Suggestions

13. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg13 DCD with ‘large cells’ DCDILC-type modified ILC type‚large cells‘ large cells single chip # columns Nx891454 # rows Ny1816 x pitch Px178,5 200 y pitch Py110 200 chip width1528 290010900 chip height2970286052004800 chip edge50 gap between chips200 - overall width [mm]10,1711,9012,2010,90 # channels per chip144128224864 # chips6641 # channels864 896864 power/control rows6664 output mux6444 # output columns881454 # output rows3 ‘ 4.5 ‘ 44 # output lines243656216

14. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg14 Module Layout – DCD (modified ILC type) modified DCD layout 180 x 110 µm 2 cells 9 rows, 16 columns x4 output multiplexing 1.7 x 3… mm 2 6 chips

15. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg15 Module Layout – DCD (large cells) large cell DCD layout 200 x 200 µm 2 cells 14 rows, 16 columns x4 output multiplexing 2.9 x 5.2 mm 2 4 chips

16. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg16 Open questions What will be the ADC resolution of the DCD? Radiation hardness –SEU hardened memory / registers needed? –Which data paths need error correction circuits? –Implement digital logic with standard cells? Implementation of cluster finding –data reduction vs. power/area –before or after 0-suppression Switcher & DCD control: –simple clock + sync. or more complicated –slow control: I 2 C or proprietary protocol (reduce number of lines!) Role of the DHH

17. H. Krüger, 11.9.08, DEPFET Workshop, Heidelberg17 To do list Estimate area and power requirements for DHP chip Organization of the design effort –Who is doing what (MPI, Barcelona, Bonn) –Common design infrastructure: technology, tools & libraries Time-line