1. 1 Progress report on the LPSC-Grenoble contribution in micro- electronics (ADC + DAC) J-Y. Hostachy, J. Bouvier, D. Dzahini, L. Galin-Martel, E. Lagorio, F-E. Rarbi, O. Rossetto, C. Vescovi

2. J-Y. Hostachy et al., LPSC-Grenoble 2 Fast Digitizer for CALICE preamp Shaper_1 Shaper_10 Memory preamp Shaper_1 Shaper_10 Memory preamp Shaper_1 Shaper_10 Memory 12 bits Fast ADC MUX 32/64  1

3. J-Y. Hostachy et al., LPSC-Grenoble 3 Why a high speed ADC ? Multiplex 32/64 to 1 ADC High speed converter: Read all channels faster More “IDLE mode” time => Saving power digital noise source from one ADC Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% idle cycle 199ms (99%) Acquisition A/D conv. DAQ IDLE MODE Extra power saving

4. 4 25 MHz, 12 bits, 2V pp Pipeline ADC Full 1.5 bit per stage

5. 5 Tests of the pipeline ADC DNL: < 1 LSB INL: < 4 LSB 2V - Power supply could be reduced => Extra Power Saved - Wide noise margin σ < 0.6 LSB

6. 6 Average Power Pulsing Budget T TC (Total Time conversion) = 40ns x 64 x 16 = 41µs MUX + ADC Power Consumption per channel = ((P ADC +P MUX ) x T TC )/200ms/64ch 141nW/channel Memory depth= 16 # of channel = 64 T c = 40 ns P ADC = 37 mW With Power pulsing P MUX = 7 mW

7. 7 stage 1 stage 2stage 10 1.5 bit FLASH 3 bits … datadelay+ digital correction 12 bits residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM Vin Back-endADC Front-endstage stage 1 2.5 bits stage 2 1.5 bit stage 10FLASH … datadelay+ digital correction 12 bits residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM Vin Back-endADC Front-endstage 1.5 bit stage 3 bit Flash 2.5 bit stage Bias stage A multi bit 2.5 bits 1st stage ADC Digital correction 8

8. J-Y. Hostachy et al., LPSC-Grenoble 8 SFDR=60dB SFDR=80dB Dynamic Element Matching effect (simulation estimate) Distortion reduced => Improvement of INL Without DEM => INL = 4 LSB With DEM => INL = 0.4 LSB Dynamic Element Matching (DEM)

9. 9 16 bit Sigma Delta DAC 16 bits with INL = +/- 4LSB Fine results but an integrated filter is needed to generate a DC signal This is not trivial, this is why we consider another architecture “C 2 C”

10. J-Y. Hostachy et al., LPSC-Grenoble 10 12 bit 4 MHz DAC for calibration (Segmented arrays of switched capacitors) This 12 bits is the basis to go forward to a 14 and 16 bit version. 12 bits with INL = +/- 0.4 LSB