1. Cortex-M3 Exceptions RTLAB. Hyeonggon Jo

2.  Exceptions Exception types & priority Abort model SVC and PendSV  Interrupt operation Pre-emption & Exit Tail-chaining & Late-arriving Exception control transfer Contents.

3.  Automatic state saving and restoring  Automatic reading of the vector table entry  Support for tail-chaining, late-arriving  Dynamic reprioritization  Configurable number of interrupt, from 1 to 240, interrupt priorities, from 3 to 8 bits  The processor supports two separate stacks Exceptions

4. Address Exception number Value 0x00000000-MSP initial value 0x000000041Reset vector ( LSB = 1 to represent thumb mode) 0x000000082NMI handler start address 0x0000000C3Hard fault handler start address ……Another exception handler start address Vector Table  Vector table offset register Aligned by size of vector table  4 records of vector table are must needed on boot image head

5. EXCEPTION TYPEPOSITIONPRIORITY -0- Reset1-3 (highest) NMI2-2 Hard Fault3 Memory Management Fault4Configurable Bus Fault5Configurable Usage Fault6Configurable -7-10- SVC11Configurable Debug Monitor12Configurable -13- PendSV14Configurable SysTick15Configurable External Interrupt16 and aboveConfigurable Exception types

6.  Priority level – from 0 to 255 Control register length – 3 ~ 8 bits (number of priorities – 8 ~ 256 level) Pre-emptive & interrupt pending Pre-emption level – 128 Exception priority MSB to control lengthRemain bits Valid number for priorityReading for 0

7. Exception priority (cont’) Binary position Pre- emption field Sub priority field Number of pre- emption priorities Number of subpriorities 0XXXXXXX.Y[7:1][0]1282 1XXXXXX.YY[7:2][1:0]644 2XXXXX.YYY[7:3][2:0]328 3XXXX.YYYY[7:4][3:0]16 4XXX.YYYYY[7:5][4:0]832 5XX.YYYYYY[7:6][5:0]464 6X.YYYYYYY[7:7][6:0]2128 7.YYYYYYYYNone[7:0]0256

8. Interrupt pending Interrupt request Interrupt Pending state Processor mode Thread mode handler mode

9.  Bus fault (BFSR, BFAR)  Memory management fault (MMSR, MMAR)  Usage fault (UFSR)  Hard fault (HFSR) Abort model

10.  To occur system call  Change privilege mode  SVC vs. SWI SVC & PendSV User program SVC kernel API Device driver peripheral OS User mode Privilege mode

11.  SVC may occur usage fault  Pend SV is Possible Pending (lowest priority) SVC & PendSV (cont’) time Context switch SYSTICK IRQ thread OS Task A IRQ OS Task B OS IRQ Task A Priority Context switch Usage fault IRQ delay

12. SVC & PendSV (cont’) Context switch SYSTICK IRQ thread Task A IRQ OS IRQ Task A Priority Context switch SVC pendSV SVC Pend svc Task B Pend svc SYSTICK

13.  Pre-emption & Exit Stacking – Un-stacking PC, xPSR, r0-r3, r12, LR Vector fetch Register update – update SP,PSR,PC,LR Interrupt sequence Pre SP(N)- N-4xPSR N-8PC N-12LR N-16R12 N-20R3 N-24R2 N-28R1 New SP (N-32) R0

14. Tail-chaining Interrupt#1 (lower priority) Interrupt#2 (higher priority) Processor state Main program ISR #1 ISR #2 Interrupt#1 event StackingUn-Stacking Interrupt exit Interrupt exit Thread mode handler mode handler mode Thread mode

15. threadException sequenceISR #2 stacking threadHandler instruction fetch Late-arriving Interrupt#1 (lower priority) Interrupt#2 (higher priority) Processor state Data bus Instruction bus Vector fetch

16. Processor activity at assertion of exception Transfer to exception processing Non-memory instructionTakes exception on completion of cycle. Load/Store singleCompletes or abandons depending on bus status. Load/Store multiple Completes or abandons current register and sets continuation counter into EPSR. Exception entryThis is a late-arriving exception. Tail-chainingThis is a late-arriving exception. Exception post ambleThis is a tail-chains exception. Exception control transfer

17. Q&A