1. 2. CMOS Op-amp설계 (1)

2. Fully balanced differential
1. Op-amp의 구조 및 특성 64
1. Op-amp의 구조 및 특성
(1) Op-amp의 구조에 따른 분류
(1-1) 입출력 형태에 따른 Op-amp
Single-ended
Op-amp
Fully differential
Op-amp
Fully balanced differential
Op-amp - +
VSS
VDD
vout
vin
Avin - +
VSS
VDD
vin
vout
Avin - +
VSS
VDD
vin
vo1
vout
vo2
1/2Avin

3. (1-2) 이득단 개수에 따른 Op-amp One-Stage Op-amp Two-Stage Op-amp65
(1-2) 이득단 개수에 따른 Op-amp
One-Stage Op-amp
Two-Stage Op-amp
Compensation Circuit
Input
Gain
Stage
Output
Stage
vin
vout
Input
Gain
Stage
2nd-Gain
Stage
Output
Stage
vin
vout
Bias
Circuit
Bias
Circuit
A (dB)
2-Stage
Pole 1 A2
Pole 2
1-Stage
2-Stage
1-Stage
Pole 1 A1 w1 w2
> A1
< A2 w2 w1
f (Hz)

4. (1-3) 단 연결 형태에 따른 Op-amp Cascode Op-amp Cascade Op-amp High gain66
(1-3) 단 연결 형태에 따른 Op-amp
Cascade Op-amp
Cascode Op-amp
Stage
vin
Stage
Stage
Stage
vout
Stage
vout
vin
High gain
Stage
High frequency

5. 2-Stage single-ended uncompensated Op-amp67
(1-4) 여러가지 Op-amp의 구조
2-Stage single-ended uncompensated Op-amp
Vin+
Vin- M5 M4 M3 M1 Cc
Vout
VDD
GND CL M7 M9 M6 M2

6. 2-Stage single-ended compensated Op-amp68
2-Stage single-ended compensated Op-amp
Vin+
Vin- M5 M4 M3 M1 Cc
Vout
VDD
GND CL M7 M9 M6 M2

7. 2-Stage single-ended Op-amp using tracking-compensation scheme69
2-Stage single-ended Op-amp using tracking-compensation scheme

8. 2-Stage single-ended Op-amp with cascode second stage70
2-Stage single-ended Op-amp with cascode second stage

9. 2-Stage single-ended Op-amp with cascode differential input stage71
2-Stage single-ended Op-amp with cascode differential input stage

10. 1-Stage input-cascode single-ended Op-amp 72
1-Stage input-cascode single-ended Op-amp
1-Stage input-cascode Telescopic Op-amp
VSS M2
Vi 1
Vi 2 M3
VO 1
VO 2

11. 1-Stage differential to single-ended folded cascode Op-amp73
1-Stage differential to single-ended folded cascode Op-amp
VDD
VSS M1 M2
Vi c M3 M9 M7
M11 M8
M10 M6 M5 M4
VB3 VO
VB1
VB2

12. 1-Stage fully differential folded cascode Op-amp(1)74
1-Stage fully differential folded cascode Op-amp(1)
VDD
VSS M1 M2
Vi n+
Vi n- M3 M9 M7
M11 M6 M5 M4
VB3
VO+
VB1
VB2
VB4
VO-

13. 1-Stage fully differential folded cascode Op-amp(2)75
1-Stage fully differential folded cascode Op-amp(2) C L M V DD 1 2 6 8 5 7 SS v in - +
BN1
out 9 10 3 4
BP1
CMFB
BP2

14. 1. Op-amp의 구조 및 특성 76
1-Stage fully differential folded cascode Op-amp with gain boosting (1)

15. 1. Op-amp의 구조 및 특성 77
1-Stage fully differential folded cascode Op-amp with gain boosting (2)

16. 1-Stage fully differential folded cascode Op-amp with CMFB circuit78
1-Stage fully differential folded cascode Op-amp with CMFB circuit
CMFB

17. Rail to rail folded cascode Op-amp79
Rail to rail folded cascode Op-amp

18. (2) Op-amp의 특성 (2-1) Ideal Op-amp - + - - + + Vin Avd80
(2) Op-amp의 특성
(2-1) Ideal Op-amp -
Vin
Avd
Differential mode gain (Avd) ->
Vout +
Common mode gain (Avc) -> 0
Vout
Avd =
Input resistance (Ri) ->
Vin +
Vin - - +
VSS
VDD
Vin Ri Ro RL
Output resistance (Ro) -> 0
Avc - +
Vin_com
Vout
Avc =
Vout

19. 혼용하며 거의 Capacitive Load를 구동하므로
1. Op-amp의 구조 및 특성 81
(2-2) Practical Op-amp
nMOS n+
Poly-Si
SiO2
P-sub
Tr소자의 Charge storage 영향  Avd 감소
Gm, Ro 의 값이 유한하므로  Avd 유한
신호 주파수 증가  Avc 증가 Ri G S D B
Vin
> 1012 W
CMOS
입력단자가 MOS의 gate에 연결되므로
vout - +
vin
Ri > 1012 W (무한대에 가깝다)
Digital
CKT CL
대부분의 CMOS Op-amp회로는 칩 내부에서 디지털회로와
혼용하며 거의 Capacitive Load를 구동하므로
Ro가 작을 필요가 없다.

20. (3-1) Power supply voltage (VDD, VSS)
1. Op-amp의 구조 및 특성 82
(3) Op-amp의 설계 parameter
(3-1) Power supply voltage (VDD, VSS)
공정 parameter 와 함께 결정됨  0.35mm(3.3V) - +
vin
vout
VSS
VDD Io CL RL
AVO
(3-2) Open loop gain ; DC 소신호 전압이득 (AVO)
dB = 20 log10 AVO
( AVO = )
Vout
Vin +
Vin -
(3-3) Power dissipation (Pdiss)
Pdiss = Power supply voltage(VDD-VSS) x DC current(Io)
(3-4) Load driving ability
Capacitive load (CL)  ( cf : CMOS mixed 회로)
Resistive load (RL)  ( cf : BJT 회로 )

21. (3-7) Unity Gain Frequency (funity) & f-3dB
1. Op-amp의 구조 및 특성 83
(3-5) Slew rate(SR)
출력전압의 시간 t 에 대한 최대변화율
Current-sourcing/sinking capability of the first stage t
Vin
Vout
Slope=
+SR
-SR
Settling time
(Ts)
1% (Final value)
C 를 충 방전 할 수 있는 최대전류로 결정
SR = Io/ Cc (V/ms)
(3-6) Settling time(Ts)
출력전압의 Final value (1%이내)에 도달시간
(3-7) Unity Gain Frequency (funity) & f-3dB
UGF : Loop gain의 크기가 1(0dB)에서의 주파수
f-3dB : Loop gain의 크기가 0.707(-3dB)에서의 주파수
AVo
(AVO) * f -3dB = f unity
f-3dB
f unity
-3dB
20log 10 1 = 0dB
20log = -3dB
0dB f

22. (3-8) Phase margin(PM) Loop gain의 크기가 1(0dB)에서의 phase와 (180o)의 차이값
1. Op-amp의 구조 및 특성 84
(3-8) Phase margin(PM)
Loop gain의 크기가 1(0dB)에서의 phase와 (180o)의 차이값
1-stage(single pole) Op-amp PM > 90o 이 되므로 항상 안정
2-stage(2-pole) Op-amp ; PM > 60o 이 되어야 안정

23. (3-9) Common mode rejection ratio (CMRR)
1. Op-amp의 구조 및 특성 85
Avc - +
Vin_com
Vout
VSS
VDD
공통모드 신호 증폭
(3-9) Common mode rejection ratio (CMRR)
공통 모드 입력 신호의 증폭 이득 제거율
Avd
CMRR =
Avc
(3-10) Power supply rejection ratio (PSRR)
전원단자에 나타나는 noise 신호등의 증폭 이득 제거율
Avc - +
Vout
VSS
VDD
Vin
VDD 잡음증폭
VSS 잡음증폭
Avd
PSRR + =
Vo / VDD
Avd
PSRR - =
Vo / VSS

24. (3-11) 공통모드 입력전압 범위 ( Input common mode voltage range ; ICMR )
1. Op-amp의 구조 및 특성 86
(3-11) 공통모드 입력전압 범위 ( Input common mode voltage range ; ICMR )
최대의 이득을 얻기 위해 모든 트랜지스터 들이 saturation영역에서 동작하기 위한
입력 전압범위
Vin - M1 M2
VDD M5 M3
VSS M4
Vin +
CMR max
VDD VDSAT VDSAT VTHp1
CMR min
VSS VTHn VDSAT VTHp1

25. (3-12) 선형 출력전압 범위 ( Linear output voltage range ; OVR )
1. Op-amp의 구조 및 특성 87
(3-12) 선형 출력전압 범위 ( Linear output voltage range ; OVR )
모든 트랜지스터 들이 saturation영역에서 동작하여 차동모드 전압이득이
최대가 되기 위한 출력 전압 범위(Output swing)
VDD
OVR min
OVR max
VSS VDSAT6
VDD VDSAT7 M7
Vout M6
VSS

26. 2. 2-stage Op-amp 2. 2-stage Op-amp (1) Uncompensated CMOS Op-amp V688
2. 2-stage Op-amp
(1) Uncompensated CMOS Op-amp
VDD M4 M5 V6 M6 M1 M2
Vin+
Vin-
Vout Cc CL M3 M9 M7
GND + + + v g v R C v g v R C v in mI in o1 1 6 m6 6 o2 L
out - - -

27. (2) Frequency Response of uncompensated Op-amp
2. 2-stage Op-amp 89
(2) Frequency Response of uncompensated Op-amp
-180 w o
<A v
(s)
-90
phase margin |A
(s)| [dB]
(0)| |p 1 | 2

28. (3) Compensated CMOS Op-amp
2. 2-stage Op-amp 90
(3) Compensated CMOS Op-amp
Vin+
Vin- M5 M4 M3 M1 Cc
Vout
VDD
GND CL M7 M9 M6 M2 g mI v in R o1 C 1 + - m6 6 o2 L
out Cc

29. (4) Compensated CMOS Op-amp
2. 2-stage Op-amp 91
(4) Compensated CMOS Op-amp g mI v in R o1 C 1 + - m6 6 o2 L
out Cc

30. (5) Compensated CMOS Op-amp
2. 2-stage Op-amp 92
(5) Compensated CMOS Op-amp

31. (6) Frequency Response of CMOS Op-amp
2. 2-stage Op-amp 93
(6) Frequency Response of CMOS Op-amp
-180 w o
<A v
(s)
-90
phase margin |A
(s)| [dB]
(0)| |p 1 | 2 |A v
(s)| [dB] w
-180 o
(0)|
<A
(s)
-90
phase
margin |p 1 | 2 z'
-270
Av(0) p1 p2 o z1

32. (7) Time Response according to Phase Margin
2. 2-stage Op-amp 94
(7) Time Response according to Phase Margin 2 4 6 8 10
0.2
0.4
0.6
0.8 1
1.2
normalized time
Q=0.1
Q=0.5
Q=1.0

33. 3. 1-stage cascode and folded cascode Op-amp
3. 1-stage cascode Op-amp 95
3. 1-stage cascode and folded cascode Op-amp
(1) 1-stage Telescopic Folded cascode Op-amp
Telescopic
Folded cascode
 Single stage amplifier
 low voltage
 No need compensation capacitance

34. (2) Frequency Response of 1-stage cascode Op-amp96
(2) Frequency Response of 1-stage cascode Op-amp + +
Vin
gm1Vin Ro CL
Vout – – |A v
(s)| [dB] w
-180 o
(0)|
<A
(s)
-90
phase
margin |p I | II M9

35. Small-signal analysis
3. 1-stage cascode Op-amp 97
(5) Gmd of single-ended folded cascode Op-amp
Small-signal analysis
VDD 10
ro4 M1 M2 M9 M7
M11 M8
M10 M6
ro5
iod= 2id ro id 12 M4 M5 4 5 13 M6 M7 4 5 VO 7 1 6
+Vi d
-Vid 2 M1 M2 3 M8
CL=10pF
+Vi d
-Vid M9 8
VB3 9 M3
M10
M11 14
VSS 11
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

36. (6) Ro of the single-ended folded cascode Op-amp
3. 1-stage cascode Op-amp 98
(6) Ro of the single-ended folded cascode Op-amp
CG출력
저항 =
ro4
ro5 M6 M7
Ro1
Ro2
Ro6
Ro7 ix ix
Ro9 M1 M2 Vx + - M8 M9
ro3
CG입력
저항 =
rs2
M10
M11
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

37. (7) CMRR of the single-ended folded cascode Op-amp
3. 1-stage cascode Op-amp 99
(7) CMRR of the single-ended folded cascode Op-amp
VDD
VSS M1 M2
Vi c M3 M9 M7
M11 M8
M10 M6 M5 M4
VB3 VO
VB1
VB2
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

38. Active 공통모드 입력전압 범위 (ICMR) Output Voltage range(OVR)
3. 1-stage cascode Op-amp
100
(9) ICMR & OVR of the single-ended folded cascode Op-amp
VDD
VSS M1 M2
Vi 1
Vi 2 M3 M9 M7
M11 M8
M10 M6 M5 M4
VB3 VO
VB1
VB2 +
VTHp - -
VTHn +
Active 공통모드 입력전압 범위 (ICMR)
Output Voltage range(OVR)
Min
Max
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

39. (10) ICMR of the NMOS & PMOS input single-ended folded cascode Op-amp
3. 1-stage cascode Op-amp
101
(10) ICMR of the NMOS & PMOS input single-ended folded cascode Op-amp
Active 공통모드 입력전압 범위
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

40. (11) 주파수 특성 of the single-ended folded cascode Op-amp
3. 1-stage cascode Op-amp
101
(11) 주파수 특성 of the single-ended folded cascode Op-amp
VDD
VSS M1 M2
Vi 1
Vi 2 M3 M9 M7
M11 M8
M10 M6 M5 M4
VB3 VO
VB1
VB2 CL
Frequency compensation : increase CL → decrease p1, no effect on p2
High Impedance Node : output node only
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

41. (12) Slew rate of the single-ended folded cascode Op-amp
3. 1-stage cascode Op-amp
102
(12) Slew rate of the single-ended folded cascode Op-amp
Slew : non-linear behavior
(단위이득회로)
(입력 Vi+의 변화에
대한 출력 Vo의 변화)
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

42. 4. Fully differential Op-amp
103
4. Fully differential Op-amp
(1) 완전 차동(fully differential) OP amp
Differential input, Differential output → Easy to cascade OP amps → Insensitive to supply noise → Requires CMFB
VDD M4
VB1 M5 M6 M7
VB2
VO+
VO-
Vi n+
Vi n- M1 M2 M9
VB3
VB3 M3
M11
VB4
VSS
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

43. 4. Fully differential Op-amp
104
(2) Rail to Rail input stage : single differential pair
 Single-polarity differential pair limit input range
 nMOS differential pair : VSS+VGS1+VDS3(sat)< input < VDD
 pMOS differential pair : VSS <input<VDD-(VGS4+VDS6(sat))

44. 4. Fully differential Op-amp
105
(3) Rail-to-rail 완전 차동 folded cascode Op-amp
* 공통모드 전압범위 및 차동모드 전압이득
최소값 :
최대값 :
공통모드
입력전압 범위
NMOS
차동 증폭단
PMOS
저주파 차동모드
전압이득Avd
Vss∼Vsn
Off On
Vsn∼Vsp
Vsp∼VDD
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

45. 4. Fully differential Op-amp
106
(4) Rail-to-rail 완전 차동 folded cascode Op-amp
* 소신호 출력저항 Ro 계산
R6 =
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

46. 4. Fully differential Op-amp
107
(5) Fully differential folded cascode OPAMP C L M V DD 1 2 6 8 5 7 SS v in - +
BN1
out 9 10 3 4
BP1
CMFB
BP2

47. 5. Gain-boosted cascode Op-amp * Gain-boosting of cascode amp
108
5. Gain-boosted cascode Op-amp
(1) Increase gain of 1-stage cascode Op-amp by gain-boosting
* Gain-boosting of cascode amp
(참조 p 56)
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

48. (2) Fully differential Gain-boosting of the feedback amp
5. Gain-boosted cascode Op-amp
109
(2) Fully differential Gain-boosting of the feedback amp
output +
output - + -
Limited output range
Improved output range
Min Vout : VDSAT(ISS1)+VDSAT1+VDSAT3
Min Vout : VDSAT(ISS2)+VDSAT5+VDSAT3+VTH5
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

49. 5. Gain-boosted cascode Op-amp
110
(3) Fully differential gain-boosting Op-amp

50. Fully differential Op-amp requires CMFB
6. 공통모드 피드백
111
6. 공통모드 피드백 (common mode feedback: CMFB) 회로
Fully differential Op-amp requires CMFB
CMFB circuits (1) Source follower + resistor divider CMFB circuit (2) Triode Transistor CMFB circuit (3) Differential pair CMFB circuit (4) Switched-capacitor CMFB circuit

51. (1) Source follower + resistor divider CMFB
6. 공통모드 피드백
112
(1) Source follower + resistor divider CMFB
Vout MIN limited to VGS7 + V(l1) l1 × (R1 + R2) > Vout swing → large l1 or large R1, R2 Usually W/L (M7, M8) very large
(2) Triode TR CMFB
M7, M8: not in the signal path → large cap no effect in differential gain
Vout MIN limited VTHn M7, M8: deep triode,
large W/L → large cap

52. (3) Differential pair CMFB
6. 공통모드 피드백
113
(3) Differential pair CMFB
Fully Differential OP amp Vout MAX limited to VDD - |VTHp| 2-stage CM → needs frequency compensation
CMFB circuit : Vcmfb=A × 0.5(V o+ + Vo-) W/L(M6,M7) very small to increase linear operating range
Vout MAX limited to VDD – VDSAT10 - |VGS6|, VoutCM set to VcmREF W/L(M6, M7, M8, M9) very small to increase linear operating range of CMFB circuit
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

53. Can be used in switching circuits No limit in Vout
6. 공통모드 피드백
114
(4) Switched-capacitor CMFB
Can be used in switching circuits No limit in Vout
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun

54. 7. 여러가지 Op-amp의 특성비교 Gain Output Swing Speed Power Dissipation Noise
115
7. 여러가지 Op-amp의 특성비교
Gain
Output
Swing
Speed
Power
Dissipation
Noise
Telescopic
Folded-Cascode
Two-Stage
Gain-Boosted
Medium
High
Highest
Low
참조 :CMOS아날로그 집접회로 설계, POSTECH, Bark Hong-Jun