1. 25 juin 2010DPallin sLHC_Tile meeting1 Tilecal VFE developments at Clermont-Ferrand June 2010 Status G Bohner, J Lecoq, X Soumpholphakdy F Vazeille, D Pallin

2. 25 juin 2010DPallin sLHC_Tile meeting2 One VFE ASIC for Tilecal VFE ASIC design : see February TILE week J Lecoq talk http://indico.cern.ch/conferenceDisplay.py?confId=84640 Specifications Large dynamic range, 16 to 17 bits Tilecal signal : 5 ns rise time, 40 ns fall time. Least significant charge: 25 fC Most significant charge: 0.8 nC (1 to 1.2 nC ?) The noise (and LSB) is half part of the smallest signal (12,5 fC) The corresponding maximum currents are: Minimum (1 LSB) of 625 nA Maximum (full scale) 40 (60 mA ?) => multi gain: 3 in this study ( 1, 8, 64) 2

3. 25 juin 2010DPallin sLHC_Tile meeting3  The base line is a current conveyor with 2 or 3 gains, shaper RC and ADC  To stay in a current mode (don't convert in voltage).  To provide multigains => To duplicate currents.  Next stages in Voltage mode.  A version with a passive shaper before the conveyor like in tile VFE has been simulated also.  Then the only difference is the way to split the signal to get a multigain.  Now R&D only for conveyor in IBM 130 nm. General design ADC Shaper Current conveyor PMT

4. 25 juin 2010DPallin sLHC_Tile meeting4 conveyor layout 1mm x 135µm Run IBM 130nm via CERN sent in foundry may 2010 Some extra delay at CERN => Tests of the produced conveyor in September 2010

5. 25 juin 2010DPallin sLHC_Tile meeting5 Simulation results 5  With a very simple shaping on each gain ( at 40ns peaking time)  Results on linearity shown during last meeting  G64 50  V/1V=5 10 -5 ; G8 500  V/1V=5 10 -4 ; G1 20mV/1V=2 10 -2  Now studies on the impact of the VFE resolution to the overall detector jet resolution Unipolar Shaping Peaking time 40 ns. Signal after shaping Linearity

6. 25 juin 2010DPallin sLHC_Tile meeting6 Simulation results 6  Studies on the impact of the VFE resolution on jet resolution  Noise on VFE  TILE VFE+ADC noise+OF G64 G1  Noise on ADC VFE LPC (10bit ADCs)  Overestimated assumption : ½ LSB  Next time : ADC noise simulation using observed noise on comparators

7. 25 juin 2010DPallin sLHC_Tile meeting7 Simulation results 7  Studies on the impact of the VFE resolution on jet resolution  Conversion charge to Energy  From - for jets use 0.9 pC/GeV. - for muons 1.15pC/GeV VFE Clermont 3 gains (64 8 1) 10 bit ADCs

8. 25 juin 2010DPallin sLHC_Tile meeting8 Simulation results 8 VFE Clermont 3 gains (64 8 1) 10 bit ADCs

9. 25 juin 2010DPallin sLHC_Tile meeting9 Simulation results 9 VFE Clermont 2 gains (64 1) 10 bit ADCs

10. 25 juin 2010DPallin sLHC_Tile meeting10 Simulation results 10 8 bits ADC not adequate to resolve muons with required S/N 10 bits ADC / 2 gains (64,1) within specifications Lower impact than tile electronics on jet resolution ( with crude assumption on ADC noise and no OF) 10 bits ADC / 3 gains (64,8,1) much better as expected Very good linearity No problem to provide 3 gains in conveyor configuration Even better if gain choice is (64, 4,1)

11. 25 juin 2010DPallin sLHC_Tile meeting11  Noise and linearity performances reach all the specifications.  VFE Tests in september.  Amplifier R&D : study going on.  Simulation of sampling + OF and « real ADC » noise going on  What is the best peaking time to choose ?  Simulation showed that a better S/N is obtained with a peaking time of 25ns.  10 bits ADC / 3 gains (64,4,1) is the best compromise from fast simu.  Is Tile community in favour of a 3 gains configuration ?  If not: why ? Conclusions

12. 25 juin 2010DPallin sLHC_Tile meeting12 BACKUP SLIDES

13. 25 juin 2010DPallin sLHC_Tile meeting13 Why a current conveyor? The signal delivered by the PMT is a current. Its conversion to a voltage is easy: With a simple impedance (resistor and/or passive shaper) U=Zi The multi gain is easy to achieve. BUT: The output impedance is Z ! => Open door for the noise, the crosstalk and the bandwidth ! Z Z With an amplifier, U=Zi again BUT: the impedance seen from the PMT is divided by the amplifier gain (now Z/Av). Reduction of the noise and crosstalk. The bandwidth is only given by the amplifier. A multi gain is impossible on this stage. The dynamic range is poor. 13Jacques Lecoq, réunion atlas LPC8 février 2010 Av

14. 25 juin 2010DPallin sLHC_Tile meeting14 Results with a very simple shaping on each gain 14 Current from the current conveyor Adding a simple shaping at 40 ns peaking time: (Only RC here, could Be adapted to CR-RC)

15. 25 juin 2010DPallin sLHC_Tile meeting15 The current conveyor solution The idea: Stay in current mode (don't convert in voltage). we need an input impedance as low as possible, an output impedance as high as possible, the possibility to handle a multi gain at the first stage. To do this copying current is sufficient: A common gate architecture is simple and efficient … 15Jacques Lecoq, réunion atlas LPC8 février 2010

16. 25 juin 2010DPallin sLHC_Tile meeting16 With a current conveyor: The advantages are: The multi gain is free, less gains are simply given by par the transistor scales. (W/L). Le current increase like the signal : The quiescent current could be low. With submicron MOS gm too small: The output impedance 1/gm is not small enough. 16Jacques Lecoq, réunion atlas LPC8 février 2010

17. 25 juin 2010DPallin sLHC_Tile meeting17 The « super » current conveyor The input is a “super common gate”. Vi is fixed by a feedback loop. The input impedance become 1/(gm0*gm3*R6) More: This architecture is self polarized. The current is twice copied. The quiescent current is small (only 1 mA for a signal current up to 50 mA or more.)  The input impedance is now very low.  It is easy to obtain a differential structure. 17Jacques Lecoq, réunion atlas LPC8 février 2010

18. 25 juin 2010DPallin sLHC_Tile meeting18 Simplified (2 gains) diagram in IBM 130nm Differential structure. Multi gain by current copy 3 gains, ratio 1, 8, 64 0-625 µA (high gain) 625µA-5mA (medium) 5-40mA (small gain) This correspond in fact to: 1,75k Ω, 217 Ω et 25 Ω. 18Jacques Lecoq, réunion atlas LPC8 février 2010 PM

19. 25 juin 2010DPallin sLHC_Tile meeting19  differential stucture  gains with current mirrors  3 gains (1, 8, 64) :  0 to 625µA (800 µA)  625µA to 5mA (6.4mA)  5mA to 40mA (5.1mA) Convoyer : schematic PMT OUT1 OUT8

20. 25 juin 2010DPallin sLHC_Tile meeting20 VFE pour Tilecale Simulation results linearity Input impedance versus magnitude Input impedance versus frequency 10MHz 40mA 1 Ω 2.34 Ω 1kHz

21. 25 juin 2010DPallin sLHC_Tile meeting21 The noise (worse case, after shaping) Noise on the highest gain: 500µV, 0.5 LSB 21Jacques Lecoq, réunion atlas LPC8 février 2010

22. 25 juin 2010DPallin sLHC_Tile meeting22 Simulation results after shaper Shaper : 5kΩ 20pF (40ns) Gain 64 : ± 50µV Gain 8 : ± 500µV Gain 1 : ± 20mV Gain : 64 σ = 500µV 1/2 LSB 1V 0.22 10 -6 out noise linearity

23. 25 juin 2010DPallin sLHC_Tile meeting23 Design : only one stage, folded cascoded One amplificator prototype

24. 25 juin 2010DPallin sLHC_Tile meeting24 Amplificator simulation

25. 25 juin 2010DPallin sLHC_Tile meeting25 Amplificator layout 370µm x 670µm Run IBM 130nm via CERN sent in foundery mai 2010