1. Hawkeye CCD University
Snapshot
February 22, 2016

2. Overview of KLI-4104 Quad-Linear Array (G, R, B, L)
High Resolution: Luma (Monochrome) Array with 5 um Pixels with 8,160 Count (Active Pixels)
Luma Channel has 4 Outputs
High Resolution: Color (RGB) Array with 10 um Pixels with 4,080 Count (Active Pixels). Buying CCD with no RGB filters for our application.
Each Color Channel has 1 Output
Two-Phase Register Clocking
Electronic Exposure Control

3. KLI-4104 Linear Array Arrangement
Overview of KLI-4104
KLI-4104 Linear Array Arrangement

4. KLI-4104 Channel Alignment
Overview of KLI-4104
KLI-4104 Channel Alignment

5. Anatomy of a CCD Sensor Photo sensitive elements - Photo diodes
Accumulation area
Horizontal readout register
Resettable floating diffusion node for charge-to-voltage conversion
Source follower buffer
Clocks for controlling charge movement

6. Anatomy of a CCD Sensor CCD Block Diagram Photo Diode &
Accumulation area
CCD Block Diagram
Direction of Shift
Transfer Clocks
Floating
Diffusion
Output
Amplifier
Serial Clocks
Serial Register
Reset Clock

7. How Does a CCD Work? Water Bucket Analogy
Photons
Photo Diodes
Transfer
Clocks
Floating Diffusion and
Output Amplifier
Serial
Clocks
Serial Register
Water Bucket Analogy

8. How Does a CCD Work? CCD Cross Section

9. Function of CCD Pre-amplifier
Low Pass
Filter
Gain IN
OUT
CCD pre-amplifier provides gain and low pass filtering
The gain is set to match the CCDs full well signal output to the ADC input range.
The filtering is to reduce broad band noise from the CCD output amplifier.

10. ADC AD9826 Block Diagram

11. ADC AD9826 Features 16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
Correlated Double Sampling
1~6x Programmable Gain
mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output w/ tri-state enable
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
Low Power CMOS: 400 mW (Typ)

12. Specific Features supported in this ADC Improve Signal Fidelity
DC Restore
Allows simple AC coupling for level shifting of input signal.
Input Offset Adjust
Allows CCD input signal to be offset to fully utilize the ADC input range.
Programmable Gain
Easy fine tuning to match input signal to ADC range
Correlated Double Sampling (CDS)
Allows removing the CCD reset offset to greatly decrease the noise of the CCD measurement.

13. Other Features simplify use of ADC
Internal Voltage Reference
Eliminates extra circuitry.
Multiplexed Byte-Wide Output w/ tri-state enable
Allows a multiplexed byte wide output bus for multiple ADC with no external circuitry
3 V/5 V Digital I/O Compatibility
Data receiver will be 3.3V logic. Allows easy data connectivity without level translation.

14. Camera Block Diagram – Single Channel, One CCD
Preamplifier
ADC
Camera Front End
Single Channel of One CCD IN
OUT
Analog Clocks
Clock Drivers
Digital Clocks
Computer
Spacecraft Interface
Image Upload Bus
Timing Generator
CPU
Camera Control
Bus
Power Supply
Memory
Spacecraft Power
Bus
FPGA
CPU

15. HawkEye Camera has 3 Output Channels per CCD, and 4 CCDs
Each linear array CCD has outputs of which 3 are used
Each ADC has 3 input channels
Total instrument has 8 bands, two per CCD
One area array CMOS Sensor used for finder scope
Total of 12 output channels to be digitized for science data

16. Camera Front End – All CCD Channels, One CCD
Preamplifiers
ADCs IN
OUT
To Computer
CCD IN
OUT
Analog Clocks
Clock Drivers
Digital Clocks
Camera Front End

17. HawkEye Camera has 1 Computer reading out all 4 CCDs
Computer supports 4 CCDs, with 4 ADCs devices digitizing 12 ADC channels total per computer
Computer supports 512 MByte of DRAM
The image from a single CCD requires 87 MBytes of memory
Each computer required to support 2 CCD images for total of 174 MBytes
Memory left for OS is 338 MBytes

18. Complete Camera Block Diagram – All CCD Channels, All CCDs
Camera Front End
Computer
Image Upload Bus
Camera Front End
Camera Control Bus
4 CCDs, 4 Clock Drivers and 12 Preamplifiers
Total of 4 CCDs for Complete System
Computer will also control the Finder Scope

19. How Does a Digital CCD Camera Operate?
CCD cameras convert light intensity to a digital number. One number for each pixel in the image
To use a CCD to create a digital image a controller or computer must control many processes in detailed sequences
A State Machine is a technique commonly used to control many processes and sequences
A camera operation timeline and description of a State Machine will follow

20. CCD Camera Operation Timeline
CCD Operation Timeline
Interleaved
All Image Lines Captured?
Image Aggregation
(and / or) Download
Flush CCD
Image Line Capture
Integration Time ?
Yes No

21. CCD Camera Operation CCD Flush
Flush CCD to prepare for image exposure
Clock transfer clocks to remove charge from photo diodes (due to dark current or photons)
Clock serial clocks to remove charge from serial register
Clock reset clock to keep floating diffusion node from saturating
Flushing CCD prepares it for image integration time

22. CCD Camera Operation Integration Time
Integration time is the time the CCD is allowed to accumulate charge in the photodiodes to create one line in an image.
Transfer clocks are kept in their default state.
Serial and reset clocks are clocked to keep dark current from building up in the serial register.
After the first line is transferred to the serial register the integration and line capture operation are interleaved.

23. CCD Camera Operation Image Line Capture
The transfer clocks are clocked to move the photodiode charge to the serial register (ending the integration time)
The serial and reset clocks are clocked to reset the floating diffusion node and then transfer one pixel at a time to the output amplifier
The ADC clocks are clocked to capture each pixel and convert it to a digital value
Process continues for each line in the image
All arrays in each CCD are read out simultaneously

24. Correlated Double Sampling is used to reduce Readout Noise by about 5X
Reference Clock
SHA
CCD
Signal +
CDS Out -
SHA
Data Clock
Correlated Double Sampling
is a method to measure electrical values such as voltages or currents that removes an undesired offset
The output of the sensor is measured twice: once during reset and once to capture the signal

25. Timing of Correlated Double Sampling Process
Reset Feedthrough
CCD
Waveform
Reference
Data
3-Channel CDS Mode Timing

26. CCD Readout Control Signals
Transfer (Vertical) Clocks
Moves charge from photodiodes to serial readout register.
Serial (Horizontal) Clocks
Moves charge along the serial register towards the floating diffusion node and output amplifier.
Reset Clock
Resets the floating diffusion node (FDN) to the RD voltage bias level.
Reset Drain Bias
Zero signal reference level for the FDN

27. CCD Control Signals Line Timing
Vertical Transfer
Shorten Integration Time
Integration Time
Exposure / Integration Time Controls
Each CCD channel has a LOGx input that will flush the Photodiodes while it is set to the active level.

28. CCD Control Signals Photodiode-to-CCD Transfer Timing
Horizontal Clocks
Transfer Clocks
Transfer clocks transfer charge from the photodiodes to the serial readout register.

29. CCD Control Signals Output Timing
Horizontal
Clocks
Reset Clock
Video Out
ADC Ref Clock
ADC Sample Clock
Two horizontal, 1 reset and 2 ADC clocks are used to capture a single pixel data value.

30. What Part of the Camera is Involved with Timing Generation?
CCD
Preamplifier
ADC IN
OUT
Analog Clocks
Clock Drivers
Digital Clocks
Computer
Spacecraft Interface
Image Data Bus
Timing Generator
CPU
Camera Control
Bus
Power Supply
Memory
Spacecraft Power
Bus
FPGA
CPU

31. CCD Control and Data Capture Requires Accurate Timing
CCD readout and ADC Clocks
For accurate exposure control the CCD and ADC clocks must be precise and stable.
Microprocessor generated clock timing is not stable enough due to interrupt handling delays and other multitasking duties of the computer.
CCD and ADC clocks must be generated in digital hardware such as an Field Programmable Gate Array (FPGA).

32. What Are FPGAs?
An array of logical elements that allow you to create many logical function from simple “AND” and “OR” gates to memory elements, even hardware based digital signal processing
The elements can be arranged to create very complex logic
Multiple channels can be clocked and data captured in parallel

33. Creating a CCD Clock in a FPGA
Counter A
Digital Comparator
A=B
Flip-Flop
Set
Clock Rising Edge Register
Reset
Clock
Out B
(A)
All logic controlled by clock A
Digital Comparator
Clock Falling Edge Register
A=B
System Clock B
(B)
One way to make clocks in a FPGA

34. Creating a CCD Clock in a FPGA - Explanation
Counter: a free running counter that counts up for each system clock rising edge.
Clock Rising Edge Register: holds the count value for which we want the CCD clock to transition to a high state.
Digital Comparator (A) compares the value in Counter and the Rising Edge Register
sets its output high when the values are equal
Otherwise the output is low.
The output of Digital Comparator (A) sets the Flip-Flop so its output goes to the high state.
The same process is followed for the Falling Edge Register and comparator
Comparator B’s output resets the Flip-Flop causing the output to go to the low state.

35. CCD Clock Drivers
A CCD Clock Driver level shifts a digital clock so it can drive a different voltage range and with increased current drive capabilities
For Example the driver accepts a 0 to 3V digital clock and outputs a clock that swings + and – 12V that can drive a large capacitive load
Most of the clocks on the KLI-4104 CCD require a 0 to 7.25V and must drive up to 660pF capacitance

36. Finderscope CMOS Sensor Data Requirements
Finder Scope uses 752 x 480 interline transfer area CCD from Micron, MT9V034.
Must take one image every 10 seconds during large image capture.
Must store 10 to 11 images per large image.
Image size is 752 x 480 x 1Byte = 361 KBytes
Total storage required is 361K x 11 = 3.97 MBytes

37. Finderscope Subsystem
The Finderscope is a separate camera that will require dedicated timing generation, clock drivers, ADC, memory and CPU
The CMOS sensor is not mounted on main CCD board, but instead is near CubeSat side of package
Camera clocks and A/D converter are all internal to CMOS sensor – interface is simple

38. The CPU Organizes Camera Operation
The CPU will organize all camera functions
The camera should be constantly listening for camera commands on the camera control bus
When commands are received without errors the camera will acknowledge the command and when appropriate change the state of the camera
Camera functions can be controlled by a software state machine

39. A Camera has many states of Operation
Examples of camera states in a state machine are:
Idle
Prepare to take an image
Initiate integration time
End exposure
Readout image
Each camera state will control hardware and the sequence of events to operate the camera.

40. State Machine Logic is used for each Task
Idle
Prepare to take an image
Initiate integration time
Last State …
State 0
State 1
State 2
State n
Camera operations are controlled by state machine logic programmed in both hardware and software.

41. State-full Control of all camera functions
Each state handles a set of camera controls to operate the camera.
Examples are:
In Camera Idle State:
Make sure mechanical shutter is closed.
Continually flush CCD sensor so it is prepared for the change to image capture state.
Poll camera control bus for commands

42. Computer Requirements
Computer must be able to acquire, store and manipulate large amount of image data
The 1800x4000 pixel image from a single pass requires 58 MBytes of memory
Max image size is 1800x6000: 87 MBytes
Each computer is required to support 2 CCD images for total of 174 MBytes
Needs a DRAM interface

43. Computer Requirements
The computer must be able to acquire, store and manipulate nearly 512 Mbyte of data in a Dynamic RAM (DRAM)
Must have adequate computational power to handle image data, camera control and high speed communications with the spacecraft simultaneously
Effective sampling rate is = 1.02 Mpixels per second for each CCD channel
Data is summed before storage – data rate saved is 900 Kpixels per second for all 4 CCDs
At this time it appears the Xilinx ZYNQ processor can keep up with real time aggregation of the data if desired