1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 Nam Pham Van

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficient Slide 2 Reduce an addition to one shift operation  On FPGA no noticeable influence  On VLSI noticeable power reduction Hex Binary CSD (Canonical Sign Digit) F9 11111001000000010 0000 0000

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Assumption: Increase the frequency better Lower the voltage  more effective Metric Design assumption Slide 3 Benchmark:

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Behavior of the metric Slide 4 Metric is better with lower voltage

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Comparison of different adders Slide 5 Values for VLSI Brent Kung adderHan Carlson adder Frequency - f500 MHz Voltage - Vdd1.0 V LibraryCOREHVTtyp10V Power P Total (W)2.7482*10 -11 2.8428*10 -11 Metric (1 / J 2 )[9.1049*10 27 ][8.8045*10 27 ]

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Design & architecture Slide 6 Brent Kung adder (a parallel prefix adder): Minimum number of nodes (implies minimum area) Efficient Suitable for VLSI Implemented version:  10 bit  11 bit  16 bit

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Filter response Slide 7

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results of ASIC design Slide 8 Mandatory values for ASIC Frequency - f 500 MHz Area - A3433.5598 μm² Power - P Dyn 1.5078 mW Power - P Leak 18.2268 nW Power - P Total 2.7482*10 -11 W # Pipeline Stages8 Metric (1 / J 2 )[9.1049*10 27 ] Synopsys Configuration: Library: COREHVTtyp10V Vdd = 1.0 V Power: set_max_dynamic_power 0 mW set_max_leakage_power 0 mW Compile: compile_ultra

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Future improvements Dynamic Voltage Scaling (DVS) Dynamic Frequency Scaling (DFS) Reducing the parasitic capacitance C Special low power design e. g. stack-effect Reduction of unnecessary switching activity Slide 9

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 10