1. 1 Status report 2011/8/12 Atsushi Nukariya

2. 2 Progress ・ FPGA -> Revision is completed. -> Obtained data from front-end chip. ・ Software

3. 3 Outline -1- Board Input Device Power Pulse Generator

4. 4 Outline -2- SiTCP GEMFE2 SiTCP

5. 5 Outline -3- 0 1 3 2 7 0 Chip Channel

6. 6 Outline -4- Chip 3 Chip 2 Chip 1 Chip 0 Capacitor 0 7 Input Channel

7. 7 Input pulse -1- ・ Check ADC value. 3us 13us Vin Delay = 1

8. 8 Input pulse -2- DAC (Threshold) 0.75 V Vin 1 3 1pF 1 2 ADC 2 3

9. 9 Test experiment -1- ・ Experiment condition is as follows. * Vin is 100mV, 150mV, 200mV ・・・ 500mV. * Threshold value is under 0.75V. ( 0.66V ) -> All events ( including noise ) can be seen. * Pulse is input on chip 0, channel 2. * 2000 events are obtained. -> Events will include empty condition. ・ Obtained data when no input is from outside. -> After 8 0x200000??, 0x7fffff?? must be seen. ・ Data are as follows. http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20110812.txt -> FPGA works correctly.

10. 10 Test experiment -2-

11. 11 Test experiment -3-

12. 12 Test experiment -4-

13. 13 Test experiment -5- ・ Vin = 350mV -> Maybe this is from mistake the number of event requested. ・ Vin = 100mV -> Scale of event is different from others. -> Data are mixed with noise.

14. 14 Test experiment -6-

15. 15 Test experiment -7-

16. 16 Frame Rate -1- ・ One PC obtains data. -> By using distributed computing system, frame rate will be higher. ・ On current board, readout speed can ’ t be achieved more than 2 MHz. -> Target readout speed was 20 MHz. ・ SiTCP can transfer data by 1 Gbps. ・ FPGA can operate with several hundred MHz. ( In recently, Achronix Semiconductor company achieved 1.5 GHz frequency speed. ) ・ In this discussion, the speed of software isn ’ t considered. ・ On current data format, data size is 32 bits.

17. 17 Frame Rate -2- ・ The case that Imaging size is 200mm x 200mm. -> 8 readout boards are needed. ・ SiTCP can transfer data by 125Mbps per a readout board. -> SiTCP clock frequency must be about 16 MHz. ( 8bits/1clock ) ・ Readout clock frequency must be one-third of SiTCP. -> However, because events aren ’ t always full, it is possible to set readout clock frequency 20 MHz. ・ Frame rate is decided by main clock. -> Main clock frequency is 10 MHz, and 1 image is created by 64 main clocks. ( Each chip has 6-bit counter. ) ・ 156,250 fps is achieved. ( Based on main clock. ) -> This value is changed by input rate of X-ray. ・ Based on SiTCP clock, 15,625 fps will be achieved.

18. 18 Software ・ Complete to create except from image process algorithm. ( http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/bin/GEMFE2Software.jar )http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/bin/GEMFE2Software.jar

19. 19 Source code FPGA http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_fpga/ Script http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_scripts/ Software ( Source code ) http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_software/ Software ( Binary ) http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/bin/GEMFE2Software.jar