1. General Tracker Meeting: Greg Iles4 December 20021 Status of the APV Emulator (APVE) First what whyhow –Reminder of what the APVE is, why we need it and how it worksSecond –Test set-up –Performance & diagnostics “real world” –Future plans, particularly integration with the rest of the Tracker and “real world” testing. APVE under test (i.e. daughter card & loop back cables) APVE status LEDs with system under test

2. General Tracker Meeting: Greg Iles4 December 20022 The APV Emulator (APVE) Task 1. –The APV25 has a 10 event buffer in de-convolution mode. –Triggers arrive in a Poisson distribution with........ 1 event every 75 nsMax rate = 1 event every 75 ns Mean period = 10  s 7000 ns –Readout of an event = 7000 ns –Finite buffer + Random triggers => Possibility of buffer overflow –BUFFER OVERFLOW => APV reset required Task 2. –The FED provides the median APV pipeline address of all its channels and compares it against a “golden” pipeline address provided by the APVE. APVE protects against buffer overflow APVE detects loss of sync in a Tracker partition What does the APVE do & why ?

3. General Tracker Meeting: Greg Iles4 December 20023 Tracker APV in deconvolution mode What does the APVE do & why ? Primary task: Preventing buffer overflow in APVs takes too long –Its takes too long to send a ‘buffers full’ signal from APVs in the tracker to Trigger Control System (TCS). –Therefore require an APV close to the TCS. Secondary task: Synchronisation check –All APV data frames include the memory cell (pipeline) address used to store the L1A data in the APV. –The pipeline address is sent to all FEDs to ensure that all APVs are in-sync. APVE 1: Full 2: Full 3: Empty 10: Empty Data frame TCS: Inhibit L1A ? Reset and L1A Busy FED: Data OK? Pipeline address (min period = 75ns) (period = 7000ns)

4. General Tracker Meeting: Greg Iles4 December 20024 Control structure APVETTCci/ex/tx APV CTCSLTCS FEC CCU Ring FED FMM Other FEDs Control & Feedback Structure....... –APVE receives Clk, BC0, L1A, L1Reset from Central & Local TCS APVE user selects CTCS, LTCS or neither via VME (i.e. just like TTCci) –APVE sends Warn, Busy, Out-Of-Sync, Ready etc to Central & Local TCS Sync Check info for FED –Pipeline address transmitted to FED via TTCci B channel. Fast feedback Pipeline address Reset & L1As Data

5. General Tracker Meeting: Greg Iles4 December 20025 FMM Tester Reports status of APV emulator and FMM input to TCS APVE test set up optional ext trigger TCS Control Clk, L1A, L1Reset, BC0, ECR, OCR VME (A24/D16) to Wishbone bridge optional ext trigger Trigger Control SystemLOCAL CENTRAL Trigger Control System CENTRAL Useful in test beams ? Ethernet cables connecting APVE signals to APVE tester daughter card FMM Status APVE ( ) and APVE tester modules ( ) are all contained within the single FPGA on the APVE. APVE Status READY, ERROR, etc Wishbone bus All modules connected within FPGA via Wishbone bus

6. General Tracker Meeting: Greg Iles4 December 20026 APVE and daughter test card LEDs APVFMM merged Switch to display either APV, FMM or merged status Synchronisation info Synchronisation info (pipeline address) sent to TTCci TCS in Central & Local TCS in Daughter test card emulate the TCS and FMM Daughter test card that that connects to the FPGA and allows us to emulate the TCS and FMM in testing APV25 daughter card All logic in Xilinx 1M gate Virtex2 FPGA TCS out Central & Local TCS out FMM in

7. General Tracker Meeting: Greg Iles4 December 20027 L1As filling APV buffers 1)READY 1) READY asserted after L1Reset (not shown) 2) enables L1As. 2) When TCS receives READY it enables L1As. 3) increases by 3 for each L1A 3) Buffer counter increases by 3 for each L1A because we are in deconvolution mode 4)WARN 4) WARN asserted 5)BUSY 5) BUSY asserted. 6) 6) Time lag in - BUSY reaching TCS - L1As reaching APVE => L1As continue after BUSY asserted L1As Buffers Pipelin e address Status

8. General Tracker Meeting: Greg Iles4 December 20028 L1As enabled as buffers empty 3) BUSY to WARN 3) APVE status switches from BUSY to WARN 1) buffer is emptied 1) An APV buffer is emptied 2) 20 to 19 2) Number of filled buffers drops from 20 to 19 4) enabling L1As 4) TCS responds by enabling L1As 5)BUSY 5) APVE immediately asserts BUSY L1As Buffers Pipelin e address Status 6) 6) Again time lag in - BUSY reaching TCS - L1As reaching APVE => L1As continue after BUSY asserted

9. General Tracker Meeting: Greg Iles4 December 20029 APVE under test L1Reset & L1A Systems enabled - APV, FMM or both TCS selected - Central or Local Status of APV, FMM or that being sent to TCS (merge). Selectable by switch (i.e.READY, WARN, etc) WARNBUSY System switching between “WARN” & “BUSY” Test system running at extremes. - L1A rate = 1 every 3 clks - Full APV buffer capacity used System tested with Central & Local TCS. APV in peak and deconvolution. Virtual & Real APV traces are displayed on the scope to visually check APVs in sync. System then pushed beyond limits. - Buffer level at which BUSY asserted increased. Check system switches to OOS

10. General Tracker Meeting: Greg Iles4 December 200210 Functionality All functionality in single Xilinx Virtex2, 1M gate FPGA –VME –VME to Internal FPGA bus (Wishbone) –I2C Interface –I2C Interface for real APV Virtual APV –Implementation of APV buffer logic to create a Virtual APV. TCS & FMM test units –Built in TCS & FMM test units which are programmable via software. Diagnostics “intelligent” –A series of registers and memories coupled with an “intelligent” response from the APVE should make it simple to diagnose why the system is OOS (Out-Of-Sync) or in ERROR. –The APVE contains circular memories that record Any change in output status and the orbit number / bunch crossing number that this occurs (4k deep) The synchronisation information for each event (2k deep)

11. General Tracker Meeting: Greg Iles4 December 200211 Performance Performance –The size of the control loop ( ) from TCS- APVE-TCS must be kept to a minimum to ensure a high Tracker efficiency. response time 1 clk cycle.The response time of the APV part of the APVE is 1 clk cycle. VHDL simulation of the APV logic maximumThe VHDL simulation of the APV logic within the FPGA provides knowledge of the APV internal buffers thus achieving maximum Tracker efficiency. minimumThe APVE resides in the same rack as the Central TCS thus keeping cable delays to a minimumReliability –System has been running for days/weeks at the maximum trigger rate in both peak and deconvolution mode. L1A TCS: L1A Inhibit ? APVE: APV buffers full ? L1A BUSY, WARN, or READY

12. General Tracker Meeting: Greg Iles4 December 200212 Experiment deadtime due to Tracker The graph shows percentage Tracker deadtime as a function of control loop size (i.e. the time for a L1A from the TCS to reach the APVE and for the BUSY signal to be transmitted The graph shows percentage Tracker deadtime as a function of control loop size (i.e. the time for a L1A from the TCS to reach the APVE and for the BUSY signal to be transmitted Below a control loop size of 3 bunch crossings the APV may use all its buffers (10) before asserting BUSY, thus keeping deadtime to a minimum Below a control loop size of 3 bunch crossings the APV may use all its buffers (10) before asserting BUSY, thus keeping deadtime to a minimum

13. General Tracker Meeting: Greg Iles4 December 200213 Conclusions & Future Conclusions –An APV emulator board has been produced and tested The inbuilt Trigger Control System may be of use for future test beams. Integration with the rest of the Tracker will now commence. Integration –Test beams –Run control software (?) Documentation –User manual XDAQ –Integrate into XDAQ –Need C++ interface

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17. General Tracker Meeting: Greg Iles4 December 200217 How does APVE work ? L1A Throttle –A counter keeps track of the number of filled APV buffers. L1A => INCREMENTS counter. Output frame => DECREMENTS the counter. Reset => CLEARS the counter. APVE must receive the same L1As and Resets as APVs within the Tracker or System fails –When the counter reaches preset values it asserts Warn followed by Busy. Synchronisation check –Header on APV data frame provides pipeline address Real APV25 Buffer counter L1A APV data frame Pipeline address to FEDs Busy DECREMENT Reset CLEAR Frame output signal Assert busy ? Header recognition APVE INCREMENT

18. General Tracker Meeting: Greg Iles4 December 200218 History of some signals recorded History: Status –Any change in output status (i.e. BUSY, WARN, etc) of the APV, FMM and the merged output sent to the Local or Central TCS is recorded along with the CMS time (Orbit, Bunch Crossing). 4k deep –Memory is 64 bits wide and 4k deep and loops back on itself. –4 bits reserved (start/stop run, TCS selected ?). History: Synchronisation information (APV pipeline address) –Real APVVHDL Simulation of APV –Real APV and VHDL Simulation of APV recorded separately to allow cross check. 2k deep –Memory is 32 bits wide and 2k deep and loops back on itself Orbit (32) Bunch Crossing (12) Status: APV (4) Status: Local TCS (4) Status: FMM (4) Status: Central TCS (4) Res (4) Event Number (24) Synchronisation Information: Pipeline Address (8) 0001 4095 0001 2047