1. Testing Semiconductor Memories
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Testing Semiconductor Memories
Cheng-Wen Wu 吳誠文
Lab for Reliable Computing
Dept. Electrical Engineering
National Tsing Hua University
Cheng-Wen Wu, LARC, NTHU

2. Outline Introduction RAM functional fault models and test algorithms
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Introduction
RAM functional fault models and test algorithms
RAM fault-coverage analysis
Cocktail-March for testing word-oriented memories
Testing multi-port RAMs
Testing CAMs
Testing flash memories
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Cheng-Wen Wu, NTHU
Cheng-Wen Wu, LARC, NTHU

3. Introduction Memory testing is a more and more important issue
RAMs are key components for electronic systems
Memories represent about 30% of the semiconductor market
Embedded memories are dominating the chip yield
Memory testing is more and more difficult
Growing density, capacity, and speed
Emerging new architectures and technologies
Embedded memories: access, diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc.
Cost drives the need for more efficient test methodologies
IFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.
Test automation is required
Failure analysis, fault simulation, ATG, and diagnostics
BIST/BIRA/BISR generation
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4. Typical RAM Production Flow
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Typical RAM Production Flow
Wafer
Full Probe Test
Laser Repair
Packaging
Pre-BI Test
Marking
Final Test
Burn-In (BI)
Post-BI Test
Shipping
QA Sample Test
Visual Inspection
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Cheng-Wen Wu, LARC, NTHU

5. Scope of RAM Testing Parametric Test: DC & AC Reliability Screening
Long-cycle testing
Burn-in: static & dynamic BI
Functional Test
Device characterization
Failure analysis
Fault modeling
Simple but effective (accurate & realistic?)
Test algorithm generation
Small number of test patterns (data backgrounds)
High fault coverage
Short test time
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6. RAM Models Behavior Level Function Level Circuit Level Layout Level
Verilog/VHDL
Function Level
Verilog/VHDL/Block diagram
Normally not synthesizable
Circuit Level
Spice/Schematic
Layout Level
GDS-II/Geometry
Who should provide the model?
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7. Memory Function Model Example
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8. RAM Fault Models (Static)
Address-Decoder Fault (AF)
No cell accessed by certain address
Multiple cells accessed by certain address
Certain cell not accessed by any address
Certain cell accessed by multiple addresses
Stuck-At Fault (SAF)
Cell (line) SA0 or SA1
Transition Fault (TF)
Cell fails to transit from 0 to 1 or 1 to 0
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9. RAM Fault Models (Static)
Bridging Fault (BF)
Short between cells
AND type or OR type
Stuck-Open Fault (SOF)
Cell not accessible due to broken line
Neighborhood Pattern Sensitive Fault (NPSF)
Active (Dynamic) NPSF
Passive NPSF
Static NPSF
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10. RAM Fault Models (Static)
Coupling Fault (CF)
State Coupling Fault (CFst)
Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given state
Inversion Coupling Fault (CFin)
Transition in coupling cell complements (inverts) coupled cell
Idempotent Coupling Fault (CFid)
Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0
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11. RAM Fault Models (Dynamic)
Recovery Fault (RF)
Sense Amplifier Recovery Fault (SARF)
Sense amp saturation after reading/writing long run of 0 or 1
Write Recovery Fault (WRF)
Write followed by reading/writing at different location resulting in reading/writing at same location
Write-after-write recovery fault
Read-after-write recovery fault
Results in functional faults---detected at high speed (e.g., GALROW/GALCOL)
Disturb Fault (DF)
Victim cell forced to 0 or 1 if we read or write aggressor cell (may be the same cell)
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12. RAM Fault Models (Dynamic)
Data Retention Fault (DRF)
DRAM
Refresh Fault
Refresh-Line Stuck-At Fault
Leakage Fault
Sleeping Sickness---loose data in less than specified hold time (typically tens of ms)
SRAM
Static Data Losses---defective pull-up
Checkerboard pattern triggers max leakage
BIST good for sync with refresh mechanism
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13. Test Time Complexity (100MHz)
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14. RAM Test Algorithm
A test algorithm (or simply test) is a finite sequence of test elements
A test element contains a number of memory operations (access commands)
Data pattern (background) specified for the Read operation
Address (sequence) specified for the Read and Write operations
A march test algorithm is a finite sequence of march elements
A march element is specified by an address order and a number of Read/Write operations
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15. Classical Test Algorithms
Zero-One Algorithm [Breuer & Friedman 1976]
Also known as MSCAN
For SAF
Solid background (pattern)
Complexity is 4N
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16. Classical Test Algorithms
Checkerboard Algorithm
Zero-one algorithm with checkerboard pattern
Complexity is 4N
For SAF and DRF
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17. Classical Test Algorithms
Galloping Pattern (GALPAT)
Complexity is 4N**2---only for characterization
All AFs,TFs, CFs, and SAFs are located
1. Write background 0;
2. For BC = 0 to N-1
{ Complement BC;
For OC = 0 to N-1, OC != BC;
{ Read BC; Read OC; }
Complement BC; }
3. Write background 1;
4. Repeat Step 2;
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18. Classical Test Algorithms
Sliding (Galloping) Row/Column/Diagonal
Based on GALPAT, but instead of a bit, a complete row, column, or diagonal is shifted
Complexity is 4N**1.5
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19. Classical Test Algorithms
Butterfly Algorithm
Complexity is 5NlogN
1. Write background 0;
2. For BC = 0 to N-1
{ Complement BC; dist = 1;
While dist <= mdist /* mdist < 0.5 col/row length */
{ Read dist north from BC;
Read dist east from BC;
Read dist south from BC;
Read dist west from BC;
Read BC; dist *= 2; }
Complement BC; }
3. Write background 1; repeat Step 2;
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20. Classical Test Algorithms
Moving Inversion (MOVI) Algorithm [De Jonge & Smeulders 1976]
For functional and AC parametric test
Functional (13N): for AF, SAF, TF, and most CF
Parametric (12NlogN): for Read access time
2 successive 2 different addresses with different data for all 2-address sequences differing in 1 bit
Repeat T2~T5 for each address bit
GALPAT---all 2-address sequences
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21. Classical Test Algorithms
Surround Disturb Algorithm
Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows
1. For each cell[p,q] /* row p and column q */
{ Write 0 in cell[p,q-1];
Write 0 in cell[p,q];
Write 0 in cell[p,q+1];
Write 1 in cell[p-1,q];
Read 0 from cell[p,q+1];
Write 1 in cell[p+1,q];
Read 0 from cell[p,q-1];
Read 0 from cell[p,q]; }
2. Repeat Step 1 with complementary data; 1
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22. Classical Test Algorithms
Zero-one and checkerboard algorithms do not have sufficient coverage
Other algorithms are too time-consuming for large RAM
Test time is the key factor of test cost
Complexity ranges from N2 to NlogN
Need linear-time test algorithms with small constants
March test algorithms
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23. March Tests Zero-One (MSCAN)
Modified Algorithmic Test Sequence (MATS) [Nair, Thatte & Abraham 1979]
OR-type address decoder fault
AND-type address decoder fault
MATS+ [Abadir & Reghbati 1983]
For both OR- & AND-type AFs and SAF
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24. March Tests Marching 1/0 [Breuer & Friedman 1976] MATS++ [Goor 1991]
For AF, SAF, and TF
MATS++ [Goor 1991]
Also for AF, SAF, and TF
Complete and irredundant
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25. March Tests March X March C [Marinescu 1982] March C- [Goor 1991]
For AF, SAF, TF, & CFin
March C [Marinescu 1982]
For AF, SAF, TF, & all CFs---redundant
March C- [Goor 1991]
Also for AF, SAF, TF, & all CFs---irredundant
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26. March Tests Limitations Solutions
Sequential faults in address decoders RF
NPSF
(9N-2) for 2-CF [Marinescu 1982]
(2NlogN+11N) for 3-CF [Cockburn 1994]
Solutions
Address sequence variation
Hopping
Pseudorandom
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27. Coverage of March Tests
Extended March C- (11N) has a 100% coverage of SOF
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28. Testing Word-Oriented RAM
Background bit is replaced by background word
MATS++:
Conventional method is to use logm+1 different backgrounds for m-bit words
m=8: , , , and
Apply the test algorithm logm+1=4 times, so complexity is 4*6N/8=3N
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29. Cocktail-March Algorithms
Motivation:
Repeating the same algorithm for all logm+1 backgrounds has redundancy
Different algorithm targets different faults
Approach:
Use multiple backgrounds in a single algorithm run
Merge and forge different algorithms and backgrounds into a single algorithm
Good for word-oriented memories
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30. March-CW Algorithm: Result: March C- for solid background (0000)
Then a 5N March for each of other standard backgrounds (0101, 0011):
Result:
Complexity is (10+5logW)N, where W is word length and N is word count
Test time is reduced by 39% if W=4, as compared with extended March C-
Improvement increases as W increases
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31. Comparison (Full Coverage)
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32. Testing NPSF NPSF test approaches 5-cell neighborhood Tiling
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Testing NPSF
NPSF test approaches
Tiling
Multi-background march
Easy BIST implementation
5-cell neighborhood
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33. NPSF Models Static NPSF (SNPSF) Passive NPSF (PNPSF)
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NPSF Models
Static NPSF (SNPSF)
BC forced to a certain state due to a certain deleted neighborhood (DN) pattern
Passive NPSF (PNPSF)
BC frozen due to a certain DN pattern
Active NPSF (ANPSF)
BC content changes due to a change in DN pattern
Change: a transition in one DN cell, with other DN cells & BC containing a certain pattern
Assumptions:
Single NPSF
Address scramble table is available
Memory is bit-oriented
Word-oriented memory is tested as multiple bit-oriented ones
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34. Test Strategy Multi-Background March
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Test Strategy
Multi-Background March
To generate all neighborhood patterns
Solid BG
(FC < 30%)
Another BG
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35. Testing PNPSF March 17N: mbist1.10 Cheng-Wen Wu, NTHU mbist1.10
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36. Data Background Generation
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Data Background Generation
Data backgrounds
BG1: all zero
BG2: Ar[0], LSB of row address
BG3: Ar[1], second bit of row address
BG4: Ar[0]Ar[1]
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37. Testing ANPSF March 12N: mbist1.10 Cheng-Wen Wu, NTHU mbist1.10
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38. Time Complexity 12 N/BG X 8 BG = 96N Detects all NPSFs mbist1.10
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12 N/BG X 8 BG = 96N
Detects all NPSFs
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39. Multi-Port Memories Popular architectures k-port (k > 1)
n-read-1-write
FIFO
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40. 2-Port Topology
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41. Inter-Port Word-Line Short
* Functional test complexity: O(N3)
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42. Inter-Port Bit-Line Short
* Functional test complexity: O(N2)
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43. Address Scrambling
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44. Reading Neighboring Cells
Read neighboring cells to detect inter-port faults: rN, rS, rE, and rW
0/1
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45. TAGS-PS
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46. Dual-Port RAM Test
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47. Compacted Dual-Port RAM Test
* Time complexity: 10N
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48. Four-Port RAM Test
* Time complexity: 17N
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49. Testing 6-Read-1-Write RAM
* Time complexity: 13N
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50. Flash Memory Testing Testing nonvolatile memories:
Masked ROM---exhaustive; pseudorandom
PROM (OTP) & EPROM---dummy row
EEPROM & flash memory---dummy row?
Testing flash memory core is hard
Customized core and I/O
Isolation (accessibility)
Reliability issues: disturbances, over program/erase, under program/erase, data retention, cell endurance, etc.
Long program/erase time
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51. Flash Memory Overview
Flash memory can be programmed and erased electrically
Has the advantages of EPROM and EEPROM
A stacked gate transistor with both the control gate (CG) and floating gate (FG):
Control gate
Floating gate
Source
Drain D n+ n+ G
P-Si S
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52. Flash Memory Program & Erase
Program(1 to 0): channel hot-electron (CHE) injection or Fowler-Nordheim (FN) electron tunneling
Erase (0 to 1): FN electron tunneling
By the entire chip or large blocks (flash erasure)
Different products have different program/erase mechanisms
Program
Erase
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53. Flash Memory Cell Types
Stacked-gate Split-gate Select-gate
Operations: Read, Program, Erase (Flash Erase)
As opposed to Read and Write in RAM
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54. Programming Scheme Comparison
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55. NOR-Array Structure
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56. NAND-Array Structure Select (drain) WL 1 WL 2 WL 3 WL 4 WL 16
Select (source)
BL i
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57. Disturbance Example (I)
NOR-Type Common Ground – Standard (Stacked Gate)
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58. Disturbance Example (II)
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59. Disturbance Example (III)
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60. Disturbance Example (IV)
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61. Gate Program Disturb Fault (GPDF)
Conditions:
1.Victim cell initial value is a logic ‘1’
2.Aggressor “10” (program)
Victim “10” (program)
Control Gate
Floating Gate
Source
Drain
Substrate G S D B
V(H)
V(L)
V(Gd)
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62. Gate Erase Disturb Fault (GEDF)
Conditions:
1.Victim cell initial value is a logic ‘0’
2.Aggressor “10” (program)
Victim “01” (erase)
Control Gate
Floating Gate
Source
Drain
Substrate G S D B
V(L)
V(H)
V(H)
V(L)
V(Gd)
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63. Drain Program Disturb Fault (DPDF)
Conditions:
1.Victim cell initial value is a logic ‘1’
2.Aggressor “10” (program) Victim “10” (program)
V(H)
During programming, erased cells on unselected rows on a bit-line that is being programmed may have a fairly deep depletion region formed under them
Electrons entering this depletion region can be accelerated by the electric field and injected over the oxide potential barrier to adjacent floating gates
V(H)
V(L)
V(Gd)
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64. Drain Erase Disturb Fault (DEDF)
Conditions:
1.Victim cell initial value is a logic ‘0’
2.Aggressor “10” (program)
Victim “01” (erase)
Control Gate
Floating Gate
Source
Drain
Substrate G S D B
V(L)
V(H)
V(H)
V(L)
V(Gd)
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65. Read Disturb Fault (RDF)
Conditions:
1. Occurs on the selected cell
2. Cell initial value is logic ‘1’
Control Gate
Floating Gate
Source
Drain
Substrate G S D B
Soft-Program
During the read operation,
hot carriers can be injected
from the channel into the FG
even if at low gate voltages
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66. Over Erase Fault (OEF)
Flash memory erase mechanism is not self-limiting
Threshold voltage can be low enough to turn the cell into a depletion-mode transistor
Fault behavior:
An unselected cell in the same bit-line has excessive source-drain leakage current
Reading that cell leads to incorrect value (like DEDF)
Cannot be programmed correctly (like TF)
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67. Basic RAM Faults for Flash Memory
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Basic RAM Faults for Flash Memory
Address-Decoder Fault (AF)
Stuck-At Fault (SAF)
Transition Fault (TF)
Stuck-Open Fault (SOF)
Bridging Fault (BF)
Coupling faults need not be considered!
Replaced by disturb faults
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68. Reliability Consideration
Reliability characteristics of floating-gate ICs depend on
Circuit density, circuit design, and process integrity
Memory array type and cell structure
Reliability stressing and testing must then be oriented toward determining the relevant failure rates for the particular array under consideration
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69. Data Retention Fault
Retention time: the time from data storage to the time at which a verifiable error is detected from any cause
Intrinsic retention times exceed millions of years in the operating temperature range
Months at 300°C
1 million years at 150 °C
120 million years at 55 °C
Data Retention Fault (DRF)
Static leakage
Built-in data retention test circuit
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70. Cell Endurance Fault
Endurance: a measure of the ability to meet data-sheet specifications as a function of accumulated program/erase cycles
Endurance limit is a result of damage to the dielectric around the floating gate caused by electric stresses
In many flash devices, the end of endurance is generally caused by hot electron trapping in the charge transport oxide
Cell Endurance Fault (CEF)
Threshold window shift due to increased program/erase cycles
Built-in stress test circuit
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71. Composite Failure Rate Determination
125°C dynamic life stress
The 125°C dynamic life stress is the standard MOS memory continuous dynamic read in a burn-in chamber
Endurance test
The endurance test is the repeated data complementing of floating-gate devices, possibly at temperature extremes
Extended data retention stress
This test is constituted by a high-temperature bake with a charge polarity that is opposite to the equilibrium state on the floating gate
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72. Typical Test Modes (Characterization)
Stress (row/column)
Reverse tunneling stress
Punch through stress
Tox stress
DC stress
Mass program
Weak erase
Leak (thin-oxide, bit-line, etc.)
Cell current; cell Vt
Margin
Etc.
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73. Test Patterns
A RAM test pattern definition includes both the data pattern and the address pattern
The time to read a pattern is the same as the time to write a pattern
For flash memories, however, the address and data pattern definitions must be segregated
It has long write times relative to the read times
Typical data patterns:
Solid, checkerboard, random, etc.
Typical address patterns:
Address increment/decrement, address complement, column/diagonal galloping, etc.
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74. Source: Saluja, et al., Int. Conf. VLSI Design, 2000
Testing GPDF
Flash
Program the first column
Read all cells except the first column
Program any column except the first
Read the first column
*Assume reading and programming are done column-wise
Source: Saluja, et al., Int. Conf. VLSI Design, 2000
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75. Source: Saluja, et al., Int. Conf. VLSI Design, 2000
Testing GEDF
Flash
Program all cells
Read all cells except the last column
Program any column except the last
Read the last column
*Assume reading and programming are done column-wise
Source: Saluja, et al., Int. Conf. VLSI Design, 2000
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76. Test Coverage: Previous Results
Fault
DCP
DCE DD EF GF
SAF
50%
100% TF
12.5%
87.5%
62.5% AF
40% 0%
44.5%
SOF
6.2%
CFst
25%
GPDF
33.3%
GEDF
75%
DEDF
DPDF
Source: Saluja, et al., Int. Conf. VLSI Design, 2000
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77. March-Based Flash Test: March-FT
{(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)}
This Flash memory is NOR type (Stacked gate).
Memory size (N) : 65536
Test length : 2(chip erase time) (word program time) (word read time)
Test time : sec
SAF : 100%
( / )
P.S.
TF : 100%
Flash Type = NOR
SOF : 100%
(65536 / 65536)
Gate Type = Stack
AF : 100%
( / )
Row Number = 256
CFst : 100%
( / )
Col Number = 256
GPD : 100%
( / )
Word Length = 1
GED : 100%
Chip erase time = 3 sec
DPD : 100%
Word program time = 9u sec
DED : 100%
Word read time = 70n sec
RD : 100%
OE : 100%
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78. Test Length (Bit-Oriented)
Notation:
F : Flash time
P : Program time
R : Read time
r : row number
c : column number
DCP
2(F) + 2r(P) + rc(R)
DCE
(F) + (c+1)r(P) + rc(R) DD
(F) + (r+1)c(P) + rc(R) EF
2(F) + (rc+2r+c-2)(P) + (2rc+r+c-3)(R) GF
2(F) + (rc+2r+c-1)(P) + (2rc+c+r-2)(R) FT
2(F) + 2rc(P) + 6rc(R)
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79. Test Length (Word-Oriented)
Word length = w:
2(F)+2rc(P)+6rc(R)+log(w)[2(F)+rc(P)+rc(R)]
Solid: 0000 (1111)
Standard: 0101 (1010), 0011 (1100)
Ex: word length w = 4
6(F) + 4rc(P) + 8rc(R)
solid background
testing time
standard background
testing time
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80. Test Algorithm Generation by Simulation (TAGS)
T(N)
Test algorithms 2N 3N 4N 5N 6N 7N 8N 9N
10N
(f); (r1)
(f); (w0); (r0)
(f); (r1,w0); (r0)
(f); (r1,w0,r0); (r0)
(f); (r1,w0,r0); (r0,w0)
(f); (r0); (r1,w0,r0); (r0,w0)
(f); (r1,w0); (f); (r1,w0,r0); (r0)
(f); (r1,w0); (r0); (f); (r1,w0,r0); (r0)
(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)
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81. Embedded Memory Testing
Memories are one of the most universal cores
In Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area; in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar, ITC-99]
In average SOC, memory cores will represent more than 90% of the chip area by 2010 [ITRS 2000]
Embedded memory testing is increasingly difficult
High bandwidth (speed and I/O data width)
Heterogeneity and plurality
Isolation (accessibility)
AC test, diagnostics, and repair
BIST is considered the best solution
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82. Embedded RAM Test Support
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83. RAM BIST Approaches Methodology Interface Patterns (address sequence)
Processor-based BIST
Programmable
Hardwired BIST
Fast
Compact
Interface
Serial (scan, )
Parallel (embedded controller; hierarchical)
Patterns (address sequence)
March
Pseudorandom
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84. Typical RAM BIST Architecture
Test Collar (MUX)
BIST Module
Controller
Comparator
Pattern
Generator
Go/No-Go
RAM Controller
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85. Transparent Serial Data-MUX
Serial March (SMarch)
From March C-
Serial interface
One BIST for all (cascaded)
One-bit read/write at a time, but one pattern per cycle
Slow
No diagnostics
Memory Cell Array
X Decoder
Y Decoder
Transparent Serial Data-MUX
Addr SI SO D Q c
Source: Nadeau-Dostie et al., IEEE D&T, Apr. 1990
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86. Syntest MBIST FSM Shared controller for multiple RAMs
Algorithms:
March C-
MOVI
March C++
Checkerboard
Shared controller for multiple RAMs
Synthesizable RTL code
FSM CE OE
WEB
ADR Control A
Data Generator D
Pass
BistFail
Finish
Analyzer Q
Source: Syntest
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87. NTHU/GUC EDO DRAM BIST
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88. DRAM Page-Mode Read-Write Cycle
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89. Programmable Memory BIST (PMBIST)
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90. PMBIST Architecture
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91. Controller and Sequencer
Microprogram
Hardwired
Shared CPU core
IEEE TAP
Sequencer (Pattern Generator)
Counter
LFSR
LUT
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92. Controller
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93. Sequencer
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94. PMBIST Test Modes Scan-Test Mode RAM-BIST Mode RAM-Diagnosis Mode
Functional faults
Timing faults (setup/hold times, rise/fall times, etc.)
Data retention faults
RAM-Diagnosis Mode
RAM-BI Mode
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95. PMBIST Controller Commands
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96. PMBIST Control Sequence
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97. BIST Area Overhead Overhead Mem size 3% 0.3% mbist1.10
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98. Processor-Based RAM BIST
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99. On-Chip Processor-Based RAM BIST
BIST program is stored in boot ROM during design phase, and memory BIST is done by executing BIST program
Address
bus
Embedded memory
CPU core
BOOT ROM
DATAI
DATAO
Control
I/O port
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100. Testing RAM Core by On-Chip CPU
mbist1.10
Testing RAM Core by On-Chip CPU
6502 assembly program that performs March C- test algorithm
data background
.org 0HFF00
LDX #$$00
LDA #$$55
M0: STA 0000,X
INX
CPX #$$FF
BNE M0
M1: LDA 0000,X
CMP #$$55
BNE ERROR
LDA #$$AA
STA 0000,X
BNE M1
write data background to memory
(W0)
(R0W1)
(R1W0)
(R0W1)
(R1W0)
(R0)
March C- algorithm
read from memory
write data background to memory
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Cheng-Wen Wu, LARC, NTHU

101. Test Speed Consideration
Processor-BIST speed is lower than dedicated BIST circuit
Total clock cycles to implement MARCH C- is O(114N)
Table instruction cycles
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102. NTHU Processor-Programmable BIST
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103. Advantages and Disadvantages
Reuse of on-chip CPU core
Might need modification
Core March elements can be implemented in hardware, allowing different March algorithms to be executed via assembly programming
Disadvantages
Some address space will be occupied by PPBIST
Area overhead
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104. PPBIST Implementation
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105. PPBIST Data Registers
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106. PPBIST Test Procedure CPU write data back ground
CPU write start/stop address
CPU write MARCH element instruction
CPU write START instruction to wrapper
BIST core
(W0)
BIST core
(R0W1)
BIST core
(R1W0)
BIST core
(R0W1)
BIST core
(R1W0)
BIST core
(R0)
write error flag
write faulty address
write faulty data
yes
compare error? no no
complete?
yes
write complete flag
CPU take over
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107. PPBIST Example Using 6502
6502 assembly program that performs March C- test algorithm under the proposed BIST scheme
START: LDA #$$55
STA 0HFFE0
LDA #$$00
STA 0HFFE1
STA 0HFFE2
LDA #$$FF
STA 0HFFE3
LDA #$$0F
STA 0HFFE4
M0: LDA #$$00
STA 0HFFE5
JSR BIST
M1: LDA #$$01
END: LDA #$$04
STA 0HFFE6
JMP FINISH
BIST: LDA #$$00
LOOP: LDA 0HFFE7
CMP #$$01
BEQ ERROR
CMP #$$FF
BNE LOOP
RTS
ERROR: LDA #$$03
STA 0HFFEA
mbist1.10
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108. PPBIST Example Addresses of the registers in the BIST experiment
March elements and the corresponding RME
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109. Experimental Results Total test time in terms of clock cycles
The sum of all the March elements' test time plus 30 clock cycles
10N clock cycles to perform March C-
Test time of each March element :
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110. Comparison of BIST Methodologies
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111. RAM BIST Compiler Use of RAM cores is increasing.
SRAM, DRAM, flash RAM
Multiple cores
RAM BIST compiler is the trend.
BRAINS (BIST for RAM in Seconds)
Proposed BIST Architecture
Memory Modeling
Command Sequence Generation
Configuration of the Proposed BIST
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Cheng-Wen Wu, LARC, NTHU

112. BRAINS Outputs Synthesizable BIST design Activation sequence
At-speed testing
Programmable March algorithms
Optional diagnosis support
BISD
Activation sequence
Test bench
Synthesis script
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Cheng-Wen Wu, NTHU

113. BIST Synthesis Flow RTL Netlist Memory GUI Library Compile Engine
RAM/BIST
Description
Parser
Compile
Engine
Memory
Library
BIST
Template
Synthesis
Cell
RTL
Netlist
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114. NTHU/GUC PMBIST Architecture
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115. PMBIST with Scan Source: Cheng, et al., DFT00 mbist1.10
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116. Sequencer address Address Generator Control Module Sequence Generatorgo
command
Command Generator
error
signature
error
info.
Error Handling Module
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Cheng-Wen Wu, NTHU

117. State Diagram of Control Module
BIST
idle
BIST
idle
BIST
active
BIST
done
BIST
done
BIST
apply
BIST
apply
For SRAM
For DRAM
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118. DRAM Page-Mode Operation
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119. Memory Specification Techniques
Memory Specifications
I/O Specification
Command Specification
Task Specification
Delay Constraint Specification
AC Parameter Specification
Support customized memories.
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Cheng-Wen Wu, NTHU

120. I/O Specification Four parameters IO_type: input, output, or inout
IO_width
IO_latency
IO_packet_length
IO_type: input, output, or inout
IO_width: port width (#bits), can be a constant or specified by user
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121. I/O Specification IO_latency: port latency mbist1.10
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122. I/O Modeling
IO_packet_length: #bits packed within a clock cycle for the port
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123. Command Specification
Specifies the memory’s instructions
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124. Task Specification Specifies a complete memory operation
A task can be a single command or a sequence of commands.
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125. Delay Constraint Specification
Specifies the minimal time interval between any two tasks
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126. AC Parameter Specification
Specifies input and output delays
Specified parameters will be inserted into the synthesis script.
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Cheng-Wen Wu, NTHU

127. Memory Specification Example
For ZBT SRAM:
Method A:
@latency D = 1;
@task write = {write};
Method B:
@latency D = 0;
@task write = {pre_write, post_write};
The BIST circuit from method A is faster than the one from method B, but it has higher area overhead
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Cheng-Wen Wu, NTHU

128. Sequence Generation
For each March element, the compiler generates the command sequence according to the read task, write task, and minimum delay between the two tasks
For example:
task read = {A}
task write = {B, C}
minimum delay between read and write = 10ns
clock period = 10 ns
Then the (rw) element becomes {A, nop, B, C}
One can also optimize the command sequence
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Cheng-Wen Wu, NTHU

129. Fast Access Mode
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130. Diagnosis Support
The BIST circuit scans out the error information (element, address, signature, and polarity) during the diagnosis mode.
Assume address 20h stuck-at 64h:
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131. Multiple RAM Cores Controller and sequencer can be shared.
Test pattern
generator
Ram Core A
sequencer
Test pattern
generator
Ram Core B
controller
sequencer
Test pattern
generator
Ram Core C
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Cheng-Wen Wu, NTHU

132. Experimental Results The Built-In Memory List
DRAM
EDO DRAM
SDRAM
DDR SDRAM
SRAM
Single-Port Synchronous SRAM
Single-Port Asynchronous SRAM
Two-Port Synchronous Register File
Dual-Port Synchronous SRAM
Micron ZBT SRAM
BRAINS can support new memory architecture easily
mbist1.10
Cheng-Wen Wu, NTHU

133. Experimental Results
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134. Experimental Results
Four single-port SRAM BIST circuits share the same controller and sequencer.
Size of the SRAM core: 8K x 16
Original
BIST area for single-port SRAM: 1438 (gates)
Total area = 1438 * 4 = 5752 (gates)
Shared
gate count: 3350
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Cheng-Wen Wu, NTHU

135. Experimental Results 8K x 16 single-port synchronous SRAM (0.25um)
Area:
Die size: x um2
BIST area: 80.1 x um2
Area overhead : 3.4%
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Cheng-Wen Wu, NTHU

136. Experimental Results 2K x 32 two-port register file (0.25um)
Die size: x um2
BIST area: x 620 um2
Area overhead: 4.5%
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137. Why RAM Diagnostics? Memory testing is more and more important
Memories are key components
Represent about 30% of the semiconductor market
Dominate the chip area/yield
Memory testing is more and more difficult
Growing density, capacity, and speed
Emerging new architectures & technologies
Growing need for embedded memories
Why diagnostics?
Yield improvement
Repair and/or design/process debugging
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138. Fault Model Subtypes
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139. NTHU-FTC BIST Architecture
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140. Test Mode
In Test Mode it runs a fixed algorithm for production test and repair
Only a few pins need to be controlled, and BGO reports the result (Go/No-Go)
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141. Fault Analysis Mode
In Fault Analysis Mode, we can apply a longer March algorithm for diagnosis
FSI captures the error information of the faulty cells
EOP format:
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142. Error Catch and Analysis
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Error Catch and Analysis
Locate the faulty cells
Identify the fault types
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Cheng-Wen Wu, LARC, NTHU

143. How to Identify Fault Type?
mbist1.10
How to Identify Fault Type?
RAM Circuit/Layout
Tester/BIST Output
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Cheng-Wen Wu, LARC, NTHU

144. March Dictionary March 11N E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 mbist1.10
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145. March Signature and Error Map
March Signature (Syndrome)
Error Map
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146. MECA System mbist1.10 Cheng-Wen Wu, NTHU mbist1.10
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147. Error Analyzer Data log parser Tester/BIST data log Fault analysis
Error maps
Fault maps
March
Dictionary
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Cheng-Wen Wu, NTHU

148. Fault Analysis Convert error maps to fault maps by the equations
Derive analysis equations from the fault dictionary
Convert error maps to fault maps by the equations
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Cheng-Wen Wu, NTHU

149. Test Algorithm Generation
Start from a base test: generated by TAGS or user-specified
Generation options reduced to read-insertions
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150. Diagnostic Resolution
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151. mbist1.10
Experimental Results
Proposed diagnosis framework has been applied to commercial embedded SRAMs
Results for a 16Kx8 embedded SRAM (FS80A020) are shown
Tester log from Credence SC212 is examined
Address remapping (logical to physical) is applied
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Cheng-Wen Wu, LARC, NTHU

152. The Total Error Bitmap mbist1.10 Cheng-Wen Wu, NTHU mbist1.10
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153. Idempotent Coupling Fault
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Fault Bitmaps
Idempotent Coupling Fault
Stuck-at 0
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Cheng-Wen Wu, LARC, NTHU

154. Redundancy and Repair
Problem: We keep shrinking the feature size and increasing the chip density and size. How do we maintain the yield?
Solutions:
Fabrication
Material, process, equipment, etc.
Design
Device, circuit, etc.
Redundancy and repair
On-line
EDAC (extended Hamming code; product code)
Off-line
Spare rows and/or columns
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Cheng-Wen Wu, NTHU

155. From BIST to BISR BIST BISD BIRA BISR BIST: built-in self-test
BIECA: built-in error catch & analysis
BISD: built-in self diagnosis
BIRA: built-in redundancy analysis
BISR: built-in self-repair
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Cheng-Wen Wu, NTHU

156. RAM Built-In Self-Repair (BISR)
MUX
BIST
Redundancy
Analyzer
Reconfiguration Mechanism
Spare Elements
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Cheng-Wen Wu, NTHU

157. RAM Redundancy 1-D: spare rows (or columns) only
SRAM
Algorithm: Must-Repair
2-D: spare rows and columns
Local and/or global spares
NP-complete problem
Conventional algorithm:
Must-Repair phase
Final-Repair phase
Repair-Most (greedy) [Tarr et al., 1984]
Fault-Driven (exhaustive, slow) [Day, 1985]
Fault-Line Covering (b&b) [Huang et al., 1990]
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158. Redundancy Architectures
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159. An SRAM with BISR
[Kim et al., ITC 98]
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160. A DRAM Redundancy Example
4 local spare rows per block
2x4=8 global spare columns
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161. Definitions Faulty line: row or column with at least one faulty cell.
A faulty line is covered if all faulty cells in the line are repaired by spare rows and/or columns.
A faulty cell not sharing any row or column with any other faulty cell is an orthogonal faulty cell.
r: number of (available) spare rows
c: number of (available) spare columns
F: number of faulty cells in a block
F’:number of orthogonal faulty cells in a block
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162. Example Block with Faulty Cells
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163. Repair-Most (RM) Construct row and column error counters.
Run BIST and construct bitmap.
Construct row and column error counters.
Run Must-Repair algorithm.
Run greedy Final-Repair algorithm.
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164. Worst-Case Bitmap (After Must-Repair)
r=2; c=4
Max F=2rc.
Max F’=r+c.
Bitmap size: (rc+c)(cr+r).
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165. Local Repair-Most (LRM)
RM is not good enough for embedded RAM.
Large storage requirement: bitmap and counters
Slow
LRM improves the performance.
Repair-Most based
Improved heuristics
Early termination rules
Concurrent BIST and BIRA
No separate Must-Repair phase
LRM reduces the storage required.
Smaller local bitmap
From (rc+c)x(cr+r) to mxn
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166. LRM Algorithm Activated by BIST whenever a faulty cell is detected.
Fault Collection (FC)
Collects faulty-cell addresses.
Constructs local bitmap.
Counts row and column errors.
Spare Allocation (SA)
Allocate spare rows or columns when bitmap is full.
Allocate spare rows or columns at end.
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167. LRM: FC and SA (1,0), (1,6), (2,4), (3,4), (5,1), (5,2) mbist1.10
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168. LRM Example
(5,2)
(5,4),(5,6),(5,7)
(7,3)
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169. Local Optimization (LO)
LMR has drawbacks:
Selecting line with largest fault count may be slow.
Multiple lines may need to be selected for repair.
Area overhead is still high.
Repair rate depends on bitmap size.
LO has a better repair rate based on same hardware overhead, i.e., a higher repair efficiency.
Fault Collection (FC)
Records faulty cells in bitmap until it is full.
Spare Allocation (SA)
Exhaustive search performed for repairing all faults.
Bitmap cleared; process repeated until done.
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170. LO: Column*/Row Selection for SA
A 1 means that the corresponding
col is selected for repair, unless empty.
Col selection vector
1. Col 5 selected for repair.
Row selection vector
2. Row 5 is selected for repair.
* Assume column selection has a lower cost than row selection.
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171. LO Example
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172. Essential Spare Pivoting (ESP)
Maintain high repair rate without using a bitmap.
Small area overhead.
Fault Collection (FC)
Collect and store faulty-cell address using row-pivot and column-pivot registers.
If there is a match for row (col) pivot, the pivot is an essential pivot.
If there is no match, store the row/col addresses in the pivot registers.
If F > r+c, the RAM is unrepairable.
Spare Allocation (SA)
Use row and column pivots for spare allocation.
Spare rows (cols) for essential row (col) pivots.
SA for orthogonal faults.
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173. ESP Example
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174. Cell Fault Size Distribution
Mixed Poisson-exponential distribution.
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175. Repair Rate Comparison
1,552 RAM blocks.
1,024x64 bits per block.
r from 6 to 10.
c from 2 to 6.
LRM bitmap: rxc.
LO bitmap: 8x4.
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176. Normalized Repair Rate
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177. Repair Rate (r=10)
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178. Normalized Repair Rate (r=6)
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179. Area Overhead Overhead is about 5-12% for 16Mb DRAM, r=8, and c=4.
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180. Computation Time (Simulated)
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