1. 6.175 Project Presentation Tony (Sen) Chang Antonio Rivera

2. Progress Completed all exercises and discussion questions All tests pass, benchmarks are in the required range

3. Division of Work (by exercise) Antonio Part 1 Exercise 1 Part 2 Exercise 3 Exercise 4 Exercise 5 Exercise 8 Presentation Tony Part 1 Exercise 2 Exercise 3 Part 2 Exercise 1 Exercise 2 Exercise 6 Exercise 7 Exercise 9 Exercise 10 Discussion Questions Presentation

4. Division of Work (by concept) Antonio L1 D-Cache Parent Protocol Processor Atomic Instructions RefDMem Calls Tony Store Queue (both parts) Message FIFO Message Routing LHUSM (both parts) Integration into 3-Cycle and 6-Stage Processors

5. The War on IPC Requirement: Reality: After implementing ReqQ, IPC is about 0.4 The war on IPC: This needs to be 2 Allows continuous cache reads Puts IPC to about ~0.6

6. The War on IPC Scoreboard needs to be of size 6: Reduces Stalls Puts IPC of cache_conf. to about 0.8 But stq.S is about ~0.75 (Supposed to be above 0.9) Train Btb on Decode Redirect Puts IPC of stq to about 0.8 Still didn’t solve all the problems

7. The One Problem What’s wrong with this code?

8. The One Problem Fifo.first() Will block no matter what! Think of while(list[0] != 0 || list.count == 0) Correct Code: Happened Twice Check for not empty first

9. Results on IPC Improvement After fixing the fifo problem, stq.S has about 0.95 IPC IPC improvements overall:

10. Bugs: Antonio Most problems came from not recognizing implicit guards For PPP, had trouble with the scheduling of rules, deadlock Had to make waitc use EHRs (double-write problem) With Lr and Sc, originally didn’t write data to cache on Sc fail Also had to set MSI state to M This fixed the deadlock problem

11. (continued) To fix bugs, relied heavily on $display statements refDMem caught a shortcut I forgot to remove in PPP (assumed only 2 caches) Relied on unit tests for L1 D-Cache and PPP

12. Improvements to the Course Some of the notation on the slides was confusing/unclear at times Ex: the slides used the variable i to represent iterating over all other caches (L22-18) This was only explicitly written on an earlier slide I originally used the Req’s ID in place of I Better Bsv Documentation / IDE Windows support?