1. System-on-Chip Design Analysis of Control Data Flow
Hao Zheng
Comp Sci & Eng
U of South Florida

2. Data & Control Edges of C Programs
C is used as a modeling as well as an implementation language.
A C program can be mapped to SW or HW.
Mapping to HW is hard.
To understand the structure of C programs.
Relations between operations in C programs
Data edges: data moved from one op. to another.
Control edge: no data xfer.

3. Control Flow Graph 1 int main(int a, b) { int r; 2 if (a > b)
else
r = b;
return r; }

4. Data Flow Graph 1 int main(int a, b) { int r; 2 if (a > b) 3 r = a;
else
r = b;
return r; }

5. Implementing Control/Data Edges
A data edge => flow of information
Must be implemented.
A control edge => result of semantics of program language
Maybe ignore or changed if the behavior remains the same.

6. Implementing Control/Data Edges
int sum(int a, b, c) {
int v1;
v1 = a + b;
v2 = v1 + c;
return v2; }

7. Basic Elements of CFG

8. Construction of CFG

9. Construction of CFG

10. Construction of CFG

11. Construction of CFG: GCD
A path in CFG corresponds to a sequence of executions of statements

12. Construction of DFG: GCD
CFG
Partial DFG

13. Construction of DFG: GCD

14. Construction of CFG/DFG
How to treat indexed variables in DFG construction?
CFG

15. Construction of CFG/DFG
Treat L as a single monolithic variable
Locations of L are treated individually

16. Translating C to HW Assumptions: Basic Idea
Scalar C programs – no pointers and arrays
Implement each statement in a clock cycle.
Basic Idea
Construct CFG and DFG
CFG => controller
DFG => datapath
Not very efficient – exist many optimization opportunities

17. HW RTL Architecture

18. Translating C to HW: Building Datapath
Each variable => a register
MUX is used if a variable is updated in multiple statements.
Each expression => a combinational logic
Conditional expressions => flags to controller
Datapath circuits and registers are connected according to data edges in DFG.

19. Translating C to HW: Building Datapath
a-b
b-a

20. Translating C to HW: Building Controller
Label CFG edges with flags from datapath and actions that DP should perform, and implement CFG as FSM.

21. Translating C to HW: Building Controller

22. Limitations Each variable mapped to a register.
A functional unit is allocated to every operator.
Performance bottleneck as a single statement is executed in a single clock cycle.
Processor is already doing this.
Can multiple statements be executed in a cycle?

23. Translating C to HW: Single-Assignment Form
Each variable is assigned exactly once.
To improve efficiency of the HW implementation.
a = a + 1;
a = a * 3;
a = a – 2;
a2 = a1 + 1;
a3 = a2 * 3;
a4 = a3 – 2;

24. Translating C to HW: Single-Assignment Form
int gcd(int a1, b1) {
while (merge(a1, a2) != merge(b1, b2)) {
a3 = merge(a1, a2);
b3 = merge(b1, b2);
if (a3 > b3)
a2 = a3 – b3;
else
b2 = b3 – a3; }
return a; }
int gcd(int a, b) {
while (a != b) {
if (a > b)
a = a – b;
else
b = b – a; }
return a; }

25. Translating C to HW: Single-Assignment Form
int gcd(int a1, b1) {
while (merge(a1, a2) != merge(b1, b2)) {
a3 = merge(a1, a2);
b3 = merge(b1, b2);
if (a3 > b3)
a2 = a3 – b3;
else
b2 = b3 – a3; }
return a; }

26. Reading Guide
Chapter 4, the CoDesign book.