1. D ATA A CQUISITION AND M ANIPULATION

2. A NALOG V S. D IGITAL Q UANTITIES 2

3. E LEMENTS OF A D ATA A CQUISITION S YSTEM 3

4. S IGNAL D IGITIZATION

5. A LIASING E FFECTS 5

6. S AMPLE AND H OLD 6

7. S AMPLE AND H OLD C HARACTERISTICS 7

8. A/D C ONVERSION B ASICS 8

9. A/D R ESOLUTION AND Q UANTIZATION E RROR 9

10. Q UANTIZATION E RROR 10

11. 16F877 A/D C ONVERTER 11

12. A NALOGUE I NPUT M ODEL 12

13. 13

14. 14

15. T IMING R EQUIREMENTS FOR O NE A/D C ONVERSION 15

16. A/D C ONVERSION S TEPS 1. Configure the A/D module: Configure analog pins/voltage reference and digital I/O (ADCON1) Select A/D input channel (ADCON0) Select A/D conversion clock (ADCON0) Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): Clear ADIF bit Set ADIE bit Set PEIE bit Set GIE bit 3. Wait the required acquisition time. 4. Start conversion: Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: Polling for the GO/DONE bit to be cleared (with interrupts enabled); OR Waiting for the A/D interrupt 6. Read A/D result register pair (ADRESH:ADRESL), clear bit ADIF, if required. 7. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. 16

17. A CQUISITION T IME 17

18. A/D C ONVERSION C LOCK The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12TAD per 10- bit conversion. The source of the A/D conversion clock is software selected. TAD must be selected to ensure a minimum TAD time of 1.6 µs. 18

19. 19

20. A/D CONVERSION TAD CYCLES 20

21. A/D R ESULT R EGISTERS 21

22. R EGISTERS A SSOCIATED WITH A/D 22