1. C OMPUTER A RITHMETIC

2. I NTRODUCTION A processor has an separate unit that is known as ALU that executes arithmetic operations. Negative numbers may be in a signed magnitude or signed complement representation. There are three ways of representing negative fixed point – binary numbers signed magnitude, signed 1’s complement or signed 2’s complement Most computers use the signed magnitude representation for the mantissa.

3. A DDITION AND S UBTRACTION WITH S IGNED –M AGNITUDE D ATA If we designate the magnitude of the two numbers by A and B. Where the signed numbers are added or subtracted, then there are eight different conditions to consider, and depending on the sign of the numbers the operation performed. These conditions are-

4. A DDITION AND S UBTRACTION WITH S IGNED –M AGNITUDE D ATA Operation Add magnitude Subtract Magnitude When A>BWhen A<BWhen A=B (+A) + (+B)+(A + B) (+A) + (-B)+ (A – B)- ( B – A)+ (A – B) (-A) + ( +B)- (A – B)+ ( B – A)+ ( A – B) (-A) + (-B)-(A + B) (+A) - (+B)+ ( A – B)- (B – A)+ ( A – B) (+A) - (-B)+( A + B) (-A) - ( +B)- (A + B) (-A) - (-B)-( A – B)+ (B – A) + (A – B)

5. A LGORITHM : A DDITION AND S UBTRACTION WITH S IGNED -M AGNITUDE D ATA - When the signs of A and B are same, add the two magnitudes and attach the sign of result is that of A. When the signs of A and B are not same, compare the magnitudes and subtract the smaller number from the larger. Choose the sign of the result to be the same as A, if A > B or the complement of the sign of A if A < B. If the two magnitudes are equal, subtract B from A and make the sign of the result will be positive.

6. H ARDWARE I MPLEMENTATION Let A and B be two registers that hold the magnitudes of the numbers, and As and Bs be two flip flops that hold the corresponding signs. The result of the operation may be transferred to a third register. The hardware implementation of above algorithm requires following- A parallel ADDER to performs micro operation A+B. A comparator circuit to establish A>B, A=B or A<B. Two parallel-subtractor circuits to perform the micro operation A-B and B-A. The sign relationship can be determined from an XOR gate with As and Bs as input.

7. A DDITION AND S UBTRACTION WITH S IGNED -M AGNITUDE D ATA The signs use an exclusive OR gate where if the output is 0, then the signs are the same. Hence, add the magnitudes of the same signed numbers. If the sum is an overflow, then a carry is stored in E where E = 1 and transferred to the flip- flop AVF, add-overflow. Otherwise, the signs are opposite and subtraction is initiated and stored in A. No overflow can occur with subtraction so the AVF is cleared. If E = 1, then A > B. However, if A = 0, then A = B and the sign is made positive. If E = 0, then A < B and sign for A is complemented.

8. H ARDWARE I MPLEMENTATION FOR SIGNED MAGNITUDE ADDITION AND SUBTRACTION B Register Complementer Parallel Adder A Register Bs AVF E As M (Mode control) Input carry Load sum Output Carry

9. F LOW C HART FOR A DD S UBTRACT

10. E XAMPLE : SIGNED MAGNITUDE A= +7  00111 B= +8  01000 As=0Bs =0 For Addition A+B As Ex-OR Bs 0 Ex-OR 0=0 EA=A+ B EA=1111 AVF=0 As= 0 A=1111  15

11. E XAMPLE : A DDITION A= +10  0 1010B= -12  1 1100 As=0Bs=1 As Ex-OR Bs=1 If we are adding A + B and sigs are different then it will be subtraction A-B So we will convert the subtrahend in 2’s comp form 1100  0100 E=0 No carry A<B 1010As=comp of As=1 + 0100 A=2’s comp of A=0010 1110

12. S UBTRACTION 7-5=2 Binary of 7= 00111 To subtract 5 from 7 we have to convert it into 2’s comp form Binary of 5=00101 2’s comp  11011 7-5= 00111 + 11011 100010 if an end carry is produced it means A>=B and we are subtracting a smaller no. from a bigger no. 1’s comp of (0101)  1010 1010 + 1= 1011

13. A NOTHER EXAMPLE 5-7 Binary of 5= 00101 To subtract 7 from 5 we have to convert it into 2’s complement form Binary of 7 = 00111 2’s comp of 7  11001 5-7 00101 + 11001 11110 If we are performing A-B and A<B then no carry will be produced.

14. A DD AND SUBTRACT USING 2’ S COMPLEMENT Register BR Complementer and parallel adder Register A V

15. A LGORITHM FOR ADDING AND SUBTRACTING NUMBERS IN SIGNED -2’ S C OMPLEMENT REPRESENTATION

16. Addition of two numbers in 2’s complement from consists of adding the number with sign bit treated the same as other bits of a number. A carry over of the sign bit position is discarded. In subtraction first take the 2’s complement of second number and added to the first number. when two numbers of n digits each are added and sum occupies n+1,we say that an overflow occurred. An overflow can be detected by inspecting the last two carries out of the addition. The over flow flip flop V is set to 1 if there is an over flow.the output carry in this case is discarded.

17. M ULTIPLICATION ALGORITHM

18. The process consists of looking at successive bits of the multiplier, LSB first. If the multiplier bit is 1, the multiplicand is copied down otherwise, zeros are copied down. The copied down in successive lines are shifted on position to the left from the previous number. Finally the numbers are added and their sum forms the product. The sign of the product is determined from the signs of the multiplicand and multiplier. If they are same the sign of the product is positive. If they are unlike, the sign of the product is negative.

19. Instead of as many number of registers as there are bits in multiplier, it is convenient to provide an adder for the summation of only two successive binary numbers. Instead of shifting the multiplicand to the left, the partial product will be shifted to the right. When the corresponding bit of multiplier is 0, there is no need to add all zeros to the partial product.

20. E XAMPLE 10011 X 11 10011 10011  shifting the bits of multiplicand left OR first right shift the partial product 10011  partial product is shifted to the left 10011

21. A RITHMETIC SHIFT OPERATION An arithmetic shift is a micro-operation that shifts a signed binary number to the left or right. An arithmetic shift-left multiplies a signed number by 2 and an arithmetic shift-right divides the number by 2. Arithmetic shift must leave the sign bit unchanged because the sign of the number remains the same when it is multiplied or divided. The left most bit in a register holds the sign bit and remaining bits hold the number.

22. T HE HARDWARE IMPLEMENTATION FOR MULTIPLY OPERATION

23. A LGORITHM -  The multiplicand is in register B and multiplier is in Q. The SC is initially set a number equal to the number of bits in multiplier.  The counter is decremented by 1 after forming each partial product.  The sum of A and B forms a partial product which is transferred to the EA register.  Both the partial product and multiplier are shifted to the right. shrEAQ.  The LSB of A is shifted into MSB of Q, The bit from E is shifted into MSB of A, and 0 is shifted into E.  In this manner the right most bit of the multiplier will be the one which must be inspected next.

24. E XAMPLE - Problem: Find the multiplication of 11001 2 and 10011 2. Solution: Let us consider that the value of multiplicand in B is =11001 2 and value of multiplier in Q is = 10011 2 Then; initially we take the value for the following: register, E=0 register, A=00000 sequence counter, SC = n = 5 = 101 2 where, n is the number of digits of the binary numbers.

26. S OLUTION - Multiplicand B=11001 EAQSC Multiplier in Q00000010011101 (5) Qn=1; Add B11001 Partial product011001 Shift Right EAQ00110011001100 (4) Qn=1; Add B11001 Partial product100101 Shift Right EAQ01001011100011 (3) Qn=0; ShR EAQ00100101110010 (2) Qn=0; ShR EAQ00010010111001 (1) Qn=1; Add B11001 Partial product011101 Shift Right EAQ00111011011000 (0) Final Product in AQ= 0111011011

27. A NOTHER EXAMPLE FOR BINARY MULTIPLIER -

28. B OOTH M ULTIPLICATION  Employs 2’s complement scheme to represent ALL signed binary integers. Means, works on both positive and negative numbers.  Reduces number of multiplication steps.  Uses both ADD & Subtract as well as right shift arithmetic.  It operates on the fact that strings of 0’s in the multiplier require no addition but just shifting, and a string of 1’s in the multiplier from bit weight 2 k to weight 2 m can be treated as 2 k+1 - 2 m

29. A LGORITHM -  Booth algorithm needs examination of the multiplier bits and shifting of the partial product.  Prior to the shifting, the multiplicand added to the partial product, subtracted from the partial product, or left unchanged by the following rules-  The multiplicand is subtracted from the partial product when we get the first least significant 1 in a string of 1's in the multiplier.  The multiplicand is added to the partial product when we get the first Q (provided that there was a previous 1) in a string of 0's in the multiplier.  The partial product does not change when the multiplier bit is the same as the previous multiplier bit.

30. H ARDWARE IMPLEMENTATION FOR BOOTH MULTIPLICATION BR Register Complementer and parallel Adder AC RegisterQR Register Qn Sequence Counter (SC) Qn +1

31. F LOW C HART OF BOOTH MULTIPLICATION

32. E XAMPLE - Problem: Find the multiplication of 11001 and 10011 using booth multiplication. Solution: Lets BR=11001 and QR=10011 Then; initially Qn+1=0 AC=00000 SC=5(no of digits)=101

33. S OLUTION - QnQn Q n+1 BR=10111 BR’+1=01001 ACQRQ n+1 SC Initial00000100110101(5) 10Sub BR01001 ashr00100110011100(4) 11ashr00010011001011(3) 01Add BR10111 11001 ashr11100101100010(2) 00ashr11110010110001(1) 10Sub BR01001 00111 ashr00011101011000(0)