1. 8051 Micro Controller

2. Microcontroller versus general-purpose microprocessor

3. Choosing a microcontroller Criteria for choosing a microcontroller

4. Comparison of 8051 Family Members

5.  In 1981, Intel Corporation introduced an 8-bit microcontroller called the 8051.  This microcontroller had 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial port, and four ports (each 8-bits wide) all on a single chip.  The 8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time.  The 8051 has a total of four I/O ports, each 8 bits wide.  Although the 8051 can have a maximum of 64K bytes of on-chip ROM.  This has led to many versions of the 8051 with different speeds and amounts of on-chip ROM marketed by more than half a dozen manufacturers.

6. OVERVIEW OF THE 8051 FAMILY

7. 8051 Pin Diagram

8. Machine Cycle and Clock Cycle The 8051 family needs 12 clock cycles for a machine cycle. The CPU takes one or more machine cycles to complete an instruction. More complex instructions require more number of machine cycles to complete the instruction.

9. Find the elapse time of the machine cycle for: (a)XTAL = 11.0592 MHz (b)XTAL = 16 MHz (c)XTAL = 20 MHz Solution: (a)11.0592 MHz / 12 = 921.6 kHz Machine cycle = 1 / 921.6 kHz = 1.085  s (b)16 MHz / 12 = 1.333 MHz Machine cycle = 1 / 1.333 MHz = 0.75  s (c)20 MHz / 12 = 1.667 MHz Machine cycle = 1 / 1.667 MHz = 0.60  s

10.  The 8051 has separate address spaces for program storage and data storage. –Depending on the type of instruction, the same address can refer to two logically and physically different memory locations. MEMORY ORGANIZATION This can be either on-chip or external depending on the value of the EA input pin. If EA is low, then the program memory is external. If EA is high, then addresses from 0000 to 0FFF will refer to on- chip memory and addresses 1000 upto FFFF refer to external memory.

11.  The 8051 has 256 bytes of RAM on-chip. –The lower 128 bytes are intended for internal data storage. –The upper 128 bytes are the Special Function Registers (SFR).  The lower 128 bytes are not to be used as standard RAM. –They house the 8051’s registers, its default stack area, and other features. Data Storage

12.  The lowest 32 bytes of the on-chip RAM form 4 banks of 8 registers each.  Only one of these banks can be active at any time.  Bank is chosen by setting 2 bits in PSW –Default bank (at power up) is bank 0 (locations 00 – 07).  The 8 registers in any active bank are referred to as R0 through R7  Given that each register has a specific address, it can be accessed directly using that address even if its bank is not the active one.

13.  The next 16 bytes – locations 20H to 2FH – form a block that can be addressed as either bytes or individual bits. –The bytes have addresses 20H to 2FH. –The bits have addresses 00H to 7FH. –Specific instructions are used for accessing the bits.  Locations 30H to 7FH are general purpose RAM. Above 7FH, there is another block of memory 80H to 0FFH in all the version of MCS51 uP

14. Register Banks  4 Register Banks — Bank0, Bank1, Bank2 and Bank3  Each Bank consists of — R0, R1, R2, R3, R4, R5, R6, R7  Bank 0 is the default upon power up of the microcontroller  Other banks can be selected by programming PSW register.

15. State the contents of RAM locations after the following program: MOVR0, #99H MOVR1, #85H MOVR2, #3FH MOVR7, #63H MOVR5, #12H After the execution of the above program we have the following: RAM location 0 has value 99HRAM location 1 has value 85H RAM location 2 has value 3FHRAM location 7 has value 63H RAM location 5 has value 12H

16. Program Status Word (PSW)  This is a very important register because it contains status bits which indicates the current state of the cpu.  PSW.7Carry (CY)  PSW.6Aux Carry (AC)  PSW.5Flag 0 (F0)  PSW.4Register Bank Select 1  PSW.3Register Bank Select 0  PSW.2Overflow (OV)  PSW.1reserved  PSW.0Even Parity Flag (P)

17. PC is a 16-bit register PC is the only register that does not have an internal address Holds the address of the memory location to fetch the program instruction Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes), external to the chip for addresses that exceed 0FFFH Program ROM may be totally external for all addresses from 0000H to FFFFH PC is automatically incremented (+1) after every instruction byte is fetched Program Counter (PC)

18. DPTR is a 16-bit register DPTR is made up of two 8-bit registers: DPH and DPL DPTR holds the memory addresses for internal and external code access and external data access (eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A ) (eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A ) DPTR is under the control of program instructions and can be specified by its 16-bit name, or by each individual byte name, DPH and DPL DPTR does not have a single internal address; DPH and DPL are each assigned an address (83H and 82H) Data Pointer (DPTR)

19. Commonly used SFRs  Accumulator, it has two names, A and ACC. Many instruction make use of the accumulator, eg: mov A,R0, push acc eg: mov A,R0, push acc  SP, always pointing to the top of the stack, increasing by 1 before write to stack, decreasing by 1 after read from stack

20. Stack and Stack Pointer (SP) SP is a 8-bit register used to hold an internal RAM address that is called the “top of the stack” Show the stack and stack pointer for the following. Assume the default stack area. MOVR6, #25H MOVR1, #12H MOVR4, #0F3H PUSH6 PUSH1 PUSH4 0B 0A 09 08 0B 0A 09 08 0B 0A 09 08 0B 0A 09 08 SP = 07 25 After PUSH 6 SP = 08 12 25 SP = 09 After PUSH 1 F3 12 25 SP = 0A After PUSH 4