1. Challenges in Hardware Logic Verification Bruce Wile IBM Server Group Verification Lead 10/25/01

2. Agenda l Five Challenges in Verification l Future Verification Trends

3. 5 Challenges in Verification 1. Better use of available simulation cycles Server Farm (Batch pool) Testcase Generators + = Billions of Sim cycles

4. 5 Challenges in Verification 1. Better use of available simulation cycles Use coverage metrics to increase new path testing. Bug discovery rate

5. 5 Challenges in Verification 2. Specification methodology ack will come on after the bias signal, followed in two cycles by the State Machines NOT MY Timing diagrams

6. 5 Challenges in Verification 2. Specification methodology Logic Description Simulation Formal Verification Model Checking

7. 5 Challenges in Verification 3. Power verification

8. 5 Challenges in Verification 3. Power verification Turn off units when not in use Verify "not in use" and no clocking FunctionCheck Low power micro- arch design and design changes Measure switching factor in chip and in "hot areas" during sim and benchmarks.

9. 5 Challenges in Verification 4. Error path testing in self healing systems Self-protecting Self-healing Self-configuring Self-optimizing

10. 5 Challenges in Verification 4. Error path testing in self healing systems For all of the legal paths for which the design must be verified, there's an order of magnitude more "illegal" paths. Verification must ensure that the hardware can: 3 Recover and continue, or 3 Take itself off-line

11. 5 Challenges in Verification 5. Detecting System Deadlocks anyServer Queue Interrupt Buffer When processor receives I/O interrupt it can't move forward until buffer releases address X, but buffer can't move forward until interrupt is completed....

12. 5 Challenges in Verification 5. Detecting System Deadlocks anyServer One solution: Abstract (hi-level) model using "Protocol" (Formal) verification to search for hangs

13. 5 Challenges in Verification 5. Choosing the right verification technology Multiple technologies to choose from, But, few experts in all Random Testcase Gen FV Deterministic

14. 5 Challenges in Verification 5. Choosing the right verification technology Education Experience in the verification cycle Strong Verification career path Continuing challenges

15. Agenda l Five Challenges in Verification l Future Verification Trends

16. Future Verification Trends n Coverage Directed Testcase Generation I-Stream Generator BHT Control Logic and BHT Array (Design under Test) Instruction Unit and Pipe Behavioral (checking and Driving BHT Array Loader BHT Array Shadow (Checking) Automatic modification of random parameters based on observed coverage

17. Future Verification Trends n Integration of Simulation with Formal Verification Logic Description Simulation Formal Verification Model Checking

18. Future Verification Trends n Integration of Simulation with Formal Verification Integration control Logic Description Simulation Formal Verification Model Checking

19. Future Verification Trends n Sharing of verification I.P. I/O PPPPPPPP Memory PPPPPPPP PPPPPPPP PPPPPPPP anyServer FPU InfiniBand Bus Architecture

20. Future Verification Trends n Sharing of verification I.P. n SOC Design will lead sharing of Verification IP n Components come from multiple sources n Need to supply verification IP n Need to have standard backplane n Need standard constructs