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Memory-efficient Turbo decoding architecture for LDPC codes

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Presentation on theme: "Memory-efficient Turbo decoding architecture for LDPC codes"— Presentation transcript:

1 Memory-efficient Turbo decoding architecture for LDPC codes
Mohammad M. Mansour and Naresh R. Shanbhag

2 Outline Introduction LDPC Codes Alternating View
Turbo Decoding Message-Passing Algorithm Decoding Architecture Ramanujan Graphs Simulation results Conclusion

3 Introduction LDPC codes were introduced by Gallager in1961 and rediscovered by Mackay-Neal and Wiberg Irregular LDPC codes yielding bit-error rates that theoretically surpass the performance of the best codes known so far This paper attempts to promote LDPC codes as practical serious competitor to Turbo codes

4 Introduction (continue)
TPMP: Two-phase message-passing algorithm Random and Stringent memory Interconnections complexity and Parallelism TDMP: Turbo-decoding messaging-passing

5 TPMP versus TDMP TDMP algorithm exhibits a faster convergence behavior and improvement in coding gain over the TPMP algorithm TDMP reduce > 75% memory overhead of the TPMP

6 LDPC codes LDPC is linear block code
If all bit node have degree c and all check nodes have degree r, the code is call regular (c,r)-LDPC codes

7 Alternating View Submatrix Hi having size n/r by n define super-code Ci 1 C2 C3 Code C can be view as intersection of ci. Punching c2 and c3 at blue 1’s to 0’s results in irregular code. C1 C

8 Construction H Hi are pseudo random permutation of the columns of H1
Irregular LDPC codes can be similarly be defined by puncturing the super-code

9 Turbo Decoding Message Passing Algorithm
Previous definition is reminiscent of parallel concatenated turbo codes SISO decoder Super-code 1 Apply the turbo decoding technique to decode LDPC code. Gallager’s message update equation & BCRJ algorithm Iteration Super-code 2 Super-code 3 Converged

10 Turbo Decoding Message Passing Algorithm (Continue)
Reduce memory requirement Fast convergence (20%~50% iteration) Reduce decoding latency Doesn’t require the saving of multiple check-bit message as is the case for the TPMP

11 Decoding Architecture
Newly generated bit messages from preceding super-codes are directly used to generate bit messages of succeeding super-codes on the same iteration

12 Decoding Architecture (continue)
Bit message are stored in circular buffer Channel value are stored in MEMλ Parameter L vs. Throughput & Complexity Interconnection complexity of mux/demux

13 Ramanujan Graph Non-trivial eigenvalues of adjacency matrix ARG(q,p) <= p is node-degree, q is number of vertices p and q are distinct odd primes If p is a quadratic non-residue modulo q, biregular bipartite graph having vertices in eachpartition and uniform node-degrees of (p+1)

14 Ramanujan Transformations
Node Spitting Edge Splitting Node Replacement + Edge Splitting Edge Merging Edge Merging + Edge splitting

15 Ramanujan Transformations (Continue)

16 Simulations Over AWGN channel with BPSK modulation
Code1: p=7, q=15, n=1440, R=1/2, using node splitting Code2: p=7, q=15, n=2880, R=1/2, using edge merging Code3: p=11, q=21, n=6048, R=1/3, using edge merging Code4:p=7, q=33, n=15840 R=0.504, using node splitting

17 Simulation Result 1

18 Simulation Result 2

19 Simulation Result 3

20 Conclusion If we want to use this method we must study architecture of Turbo Code Study Algebra and Number Theory (for code search or code design) Build a simulation model to evaluate our code and architecture


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