1. Ass. Prof. Dr Masri Ayob TK 2123 Lecture 14: Instruction Set Architecture Level (Level 2)

2. 25 February 2016Prepared by: Dr Masri Ayob 2 ISA Level OS level – ISA level - Microarchitecture level. Historically, ISA level was developed before any of the other levels (originally the only level). Sometimes referred as “the architecture” of a machine or “assembly language” (incorrect). Interface between software and hardware. The ISA level defines the interface between the compilers and hardware.

3. 25 February 2016Prepared by: Dr Masri Ayob 3 ISA Level The ISA level is the interface between the compilers and the hardware.

4. 25 February 2016Prepared by: Dr Masri Ayob 4 ISA Level Is defined by how the machine appears to a machine language programmer. No person does machine language programming. Redefined : ISA-level code is what a compiler outputs. The compiler writer has to know: Memory model Registers Data type Addressing mode Instruction set.

5. 25 February 2016Prepared by: Dr Masri Ayob 5 Memory Models What order do we read numbers that occupy more than one byte e.g. (numbers in hex to make it easy to read) 12345678 can be stored in 4x8bit locations as follows

6. 25 February 2016Prepared by: Dr Masri Ayob 6 Memory Models (example) AddressValue (1)Value(2) 1841278 1853456 1865634 1867812 i.e. read top down or bottom up?

7. 25 February 2016Prepared by: Dr Masri Ayob 7 Memory Models The problem is called Endian The system on the left has the most significant byte in the smallest address: Big-endian The system on the right has the least significant byte in the smallest address: Little-endian

8. 25 February 2016Prepared by: Dr Masri Ayob 8 Example of C Data Structure

9. 25 February 2016Prepared by: Dr Masri Ayob 9 Standard…What Standard? Pentium (80x86), VAX are little-endian IBM 370, Motorola 680x0 (Mac), and most RISC are big-endian Internet is big-endian.

10. 25 February 2016Prepared by: Dr Masri Ayob 10 What is an Instruction Set? The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes

11. 25 February 2016Prepared by: Dr Masri Ayob 11 Elements of an Instruction Operation code (Opcode) Do this…i.e. the task to be performed Source Operand reference To this..i.e. the data to be operated on Result Operand reference Put the answer here….. Next Instruction Reference When you have done that, do this...

12. 25 February 2016Prepared by: Dr Masri Ayob 12 Where have all the Operands Gone? Main memory (or virtual memory or cache) CPU register I/O device

13. 25 February 2016Prepared by: Dr Masri Ayob 13 Instruction Cycle State Diagram

14. 25 February 2016Prepared by: Dr Masri Ayob 14 Instruction Representation In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used e.g. ADD, SUB, LOAD Operands can also be represented in this way ADD A,B Usually there are not enough bits in one byte to store enough instructions and addresses: Instructions stored in more than one byte.

15. 25 February 2016Prepared by: Dr Masri Ayob 15 Simple Instruction Format

16. 25 February 2016Prepared by: Dr Masri Ayob 16 Number of Addresses (a) 3 addresses Operand 1, Operand 2, Result a = b + c; May be a forth - next instruction (usually implicit) Not common Needs very long words to hold everything

17. 25 February 2016Prepared by: Dr Masri Ayob 17 Number of Addresses (b) 2 addresses One address doubles as operand and result a = a + b Reduces length of instruction Requires some extra work Temporary storage to hold some results

18. 25 February 2016Prepared by: Dr Masri Ayob 18 Number of Addresses (c) 1 address Implicit second address Usually a register (accumulator) Common on early machines

19. 25 February 2016Prepared by: Dr Masri Ayob 19 Number of Addresses (d) 0 (zero) addresses All addresses implicit Uses a stack e.g. push a push b add pop c

20. 25 February 2016Prepared by: Dr Masri Ayob 20 How Many Addresses More addresses More complex (powerful?) instructions More registers Inter-register operations are quicker Fewer instructions per program Fewer addresses Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions

21. 25 February 2016Prepared by: Dr Masri Ayob 21 Design Decisions (1) Operation issues: How many ops? What can they do? How complex are they? Data types Instruction formats Length of op code field Number of addresses

22. 25 February 2016Prepared by: Dr Masri Ayob 22 Design Decisions (2) Registers Number of CPU registers available Which operations can be performed on which registers? Addressing modes (later…) RISC v CISC

23. 25 February 2016Prepared by: Dr Masri Ayob 23 Addressing Modes Instructions can be categorized according to their method of addressing the hardware registers and/or memory. Implied Addressing Register Addressing Immediate Addressing Direct Addressing Register Indirect Addressing Combined Addressing Modes. The various ways of addressing data in an instruction are known as addressing mode.

24. 25 February 2016Prepared by: Dr Masri Ayob 24 Implied Addressing The addressing mode of certain instructions is implied by the instruction’s function. For example: the STC (set carry flag) instruction deals only with the carry flag the DAA (decimal adjust accumulator) instruction deals with the accumulator.

25. 25 February 2016Prepared by: Dr Masri Ayob 25 Register Addressing The accumulator is implied as a second operand. For example, the instruction CMP E may be interpreted as 'compare the contents of the E register with the contents of the accumulator.

26. 25 February 2016Prepared by: Dr Masri Ayob 26 Immediate Addressing These instructions have data assembled as a part of the instruction itself. For example, the instruction CPI 'C' may be interpreted as ‘compare the contents of the accumulator with the letter C.

27. 25 February 2016Prepared by: Dr Masri Ayob 27 Direct Addressing These instructions directly specify the memory address of the operand. Example: JMP 1000 H causes a jump to the address 1000 H by replacing the current contents of the PC with the new value 1000 H. LDA 2000H will load the contents of memory location 2000H into the accumulator.

28. 25 February 2016Prepared by: Dr Masri Ayob 28 Register Indirect Addressing These instructions reference memory via a register pair. For example: MOV M,C moves the contents of the C register into the memory location pointed by the H and L register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair.

29. 25 February 2016Prepared by: Dr Masri Ayob 29 Combined Addressing Modes Some instructions use a combination of addressing modes. A CALL instruction, for example, combines direct addressing and register indirect addressing. The direct address in a CALL instruction specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL instruction pushes the current contents of the program counter into the memory location specified by the stack pointer..

30. 25 February 2016Prepared by: Dr Masri Ayob 30 Discussion of Addressing Modes A comparison of addressing modes.

31. 25 February 2016Prepared by: Dr Masri Ayob 31 Timing Effects of Addressing Modes Addressing modes affect both: the amount of time required for executing an instruction. the amount of memory required for its storage. For example, instructions that use implied or register addressing, execute very quickly since they deal directly with the processor’s hardware or with data already present in hardware registers. the entire instruction can be fetched with a single memory access. The number of memory accesses required is the greatest factor in determining execution timing.

32. 25 February 2016Prepared by: Dr Masri Ayob 32 Timing Effects of Addressing Modes More memory accesses require more execution time. A CALL instruction, for example, requires five memory accesses: three to access the entire instruction and two more to push the contents of the program counter onto the stack.

33. 25 February 2016Prepared by: Dr Masri Ayob 33 Types of Operand Addresses Numbers Integer/floating point Characters ASCII etc. Logical Data Bits or flags

34. 25 February 2016Prepared by: Dr Masri Ayob 34 Pentium Data Types 8 bit Byte 16 bit word 32 bit double word 64 bit quad word Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4

35. 25 February 2016Prepared by: Dr Masri Ayob 35 Types of Instruction Operation Data Transfer (data movement) Arithmetic Logical Conversion I/O System Control Program Control

36. 25 February 2016Prepared by: Dr Masri Ayob 36 Data Transfer (Data Movement) Specify Source Destination Amount of data May be different instructions for different movements e.g. IBM 370 Or one instruction and different addresses e.g. VAX E.g. MOV A,B Move 8-bit data from register B to accumulator A.

37. 25 February 2016Prepared by: Dr Masri Ayob 37 Data Transfer (Data Movement) Data Movement Instructions are the most frequently used and computer designers provide a lot of flexibility to these instructions. E.g. Intel 8085 provides data transfer between: Register-to-register Register-to-memory Memory-to-register Stack operation.

38. 25 February 2016Prepared by: Dr Masri Ayob 38 Arithmetic Add, Subtract, Multiply, Divide E.g. ADD C Add the content of register C to the content of accumulator A. Signed Integer Floating point ? May include Increment (a++) Decrement (a--) Negate (-a)

39. 25 February 2016Prepared by: Dr Masri Ayob 39 Shift and Rotate Operations

40. 25 February 2016Prepared by: Dr Masri Ayob 40 Logical Bitwise operations AND, OR, NOT Example: ANA B  A= A AND B

41. 25 February 2016Prepared by: Dr Masri Ayob 41 Conversion E.g. Binary to Decimal

42. 25 February 2016Prepared by: Dr Masri Ayob 42 Input/Output May be specific instructions E.g. IN 12  Read input data from port location 12 May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA)

43. 25 February 2016Prepared by: Dr Masri Ayob 43 Systems Control Privileged instructions CPU needs to be in specific state Ring 0 on 80386+ Kernel mode For operating systems use

44. 25 February 2016Prepared by: Dr Masri Ayob 44 Program Control Instructions Branch/Jump e.g. branch to x if result is zero JZ Skip e.g. increment and skip if zero ISZ Register1 Branch xxxx Subroutine call E.g. CALL sum Return from subroutine E.g. RET

45. 25 February 2016Prepared by: Dr Masri Ayob 45 Nested Procedure Calls

46. 25 February 2016Prepared by: Dr Masri Ayob 46 Use of Stack

47. 25 February 2016Prepared by: Dr Masri Ayob 47 The Pentium 4’s primary registers.

48. 25 February 2016Prepared by: Dr Masri Ayob 48 The Pentium 4 Instruction Formats The Pentium 4 instruction formats.

49. 25 February 2016Prepared by: Dr Masri Ayob 49 Example of 8051 Instructions More……

50. 25 February 2016Prepared by: Dr Masri Ayob 50 Thank you Q&A