1. Computer Organization (Review of Prerequisite Material)

2. Program Specification int a, b, c, d;... a = b + c; d = a - 100; Source ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a Assembly Language ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d

3. Machine Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Assembly Language 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 10111001010000…0 10100110001100…0 10111001101100…1 Machine Language

4. von Neumann Computer Arithmetic-Logical Unit (ALU) Arithmetic-Logical Unit (ALU) Control Unit Primary Memory (Executable Memory) Primary Memory (Executable Memory) Address Data

5. Primary Memory Unit MAR MDR Command 0 1 2 n-1 123498765 Read Op: 1234 1. Load MAR with address read 2. Load Command with “read” 98765 3. Data will then appear in the MDR

6. Control Unit 3046 3050 3054 3058 Primary Memory Fetch Unit Decode Unit Execute Unit PC IR Control Unit load R3,b load R4,c add R3,R4 store R3,a 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 load R4, c 3050

7. Control Unit Operation PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase }; Fetch phase: Instruction retrieved from memory Execute phase: ALU op, memory data reference, I/O, etc.

8. The ALU R1 R2 Rn... Status Registers Functional Unit Left Operand Right Operand Result To/from Primary Memory load R3,b load R4,c add R3,R4 store R3,a

9. Bootstrapping Bootstrap loader (“boot sector”) Primary Memory 1 0x0001000 Fetch Unit Decode Unit Execute Unit 0000100 … … PC IR BIOS loader 0x0000100

10. Bootstrapping Bootstrap loader (“boot sector”) Primary Memory Loader 1 2 Fetch Unit Decode Unit Execute Unit 0001000 … … PC IR BIOS loader 0x0000100 0x0001000 0x0008000

11. Bootstrapping Bootstrap loader (“boot sector”) Primary Memory Loader OS 1 2 3 Fetch Unit Decode Unit Execute Unit 0008000 … … PC IR BIOS loader 0x0000100 0x0001000 0x0008000 0x000A000

12. Bootstrapping Bootstrap loader (“boot sector”) Primary Memory Loader OS 1 2 3 4. Initialize hardware 5. Create user environment 6. … Fetch Unit Decode Unit Execute Unit 000A000 … … PC IR BIOS loader 0x0000100 0x0001000 0x0008000 0x000A000

13. Address Data Von Neumann Computer Arithmetic-Logical Unit (ALU) Arithmetic-Logical Unit (ALU) Control Unit Primary Memory (Executable Memory) Primary Memory (Executable Memory) Device

14. Device Organization Application Program Device Controller Device Software in the CPU Device manager Program to manage device controller Supervisor mode software Abstract I/O Machine

15. Device Controller Interface Command Status Data 0 Data 1 Data n-1 Logic busydoneError code... busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)

16. Performing a Write Operation while(deviceNo.busy || deviceNo.done) ; deviceNo.data[0] = deviceNo.command = WRITE; while(deviceNo.busy) ; deviceNo.done = TRUE; Devices much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while I/O is in process

17. CPU-I/O Overlap CPU Device … Ready Processes CPU Device … Ready Processes I/O Operation CPU Device … Ready Processes Uses CPU

18. Determining When I/O is Complete CPU Device Interrupt Pending CPU incorporates an “interrupt pending” flag When device.busy  FALSE, interrupt pending flag is set Hardware “tells” OS that the interrupt occurred Interrupt handler part of the OS makes process ready to run

19. Control Unit with Interrupt (Hardware) PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1] }; memory[1] contains the address of the interrupt handler

20. Interrupt Handler (Software) interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */ deviceHandler(int i) { finishOperation(); returnToScheduler(); }

21. A Race Condition saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+NumberOfRegisters+i] = StatusRegister[i]; } PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest && InterruptEnabled) { disableInterupts(); memory[0] = PC; PC = memory[1] };

22. Revisiting the trap Instruction (Hardware) executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2... case n: PC = memory[1000+n];// Trap handler n }; The trap instruction dispatches a trap handler routine atomically Trap handler performs desired processing “A trap is a software interrupt”