1. Key Observation Adjacencies in the K-Map
011
111 BC A 00 01 11 10
010
110
000
010 1 10
100 B
001 1
001 01 1 1
101
101 C C
000
100 A
Any two adjacant cells in the K-map differ in exactly one variable.
The uniting theorem can be applied when adjacent cells contain (function =1)
to eliminat the changing variable.

2. Design Examples Two Bit Comparator Truth Table Block Diagram
Design Steps:
1- Simplify to reduce cost (three 4-variable K-maps, one for each output)
2- Implement using a suitable design style
(e.g. 2-level AND-OR, NAND-NAND, or multilevel techniques)

3. Design Examples Two Bit Comparator (continued)
F1 = A' B' C' D' + A' B C' D + A B C D + A B' C D'
F2 = A' B' D + A' C
F3 = B C' D' + A C' + A B D'
f1 = AC(BD+bd) + ac(bd+BD) = (AC+ac) (bd+BD)
= (a c) (b d)

4. Design Examples
Two-Bit Adder
Truth Table
Block Diagram

5. Design Example Two-Bit Adder (Continued) X = A C + B C D + A B D00 01 11 10 1 C CD A D B
K-map for X AB 00 01 11 10 1 C CD A D B
K-map for Y AB 00 01 11 10 1 C CD A D B
K-map for Z
X = A C + B C D + A B D
Z = B D' + B' D = B xor D
Y = A' B' C + A B' C' + A' B C' D + A' B C D' + A B C' D' + A B C D

6. 5-Variable K-Maps Constructed from two 4-variable K-Maps. A = 0 A = 1
100
101
111
110 B C
ABC
000
001
011
010 00 01 11 10 D DE E 1
f = bCDE + Bd C
100
101
111
110 B
ABC
000
001
011
010 00 01 11 10 D DE 1 E
g = ABe + Bce + bE

7. ƒ(A,B,C,D,E) = C E + A B' E + B C' D' E' + A' C' D E'
5-Variable K-Maps
Another View
ƒ(A,B,C,D,E) = Sm(2,5,7,8,10,13,15,17,19,21,23,24,29 31)
ƒ(A,B,C,D,E) = C E + A B' E + B C' D' E' + A' C' D E'

8. 6-Variable K-Maps ƒ(A,B,C,D,E,F) = Sm(2,8,10,18,24, 26,34,37,42,45,50,
53,58,61)

9. 6-Variable K-Maps ƒ(A,B,C,D,E,F) = Sm(2,8,10,18,24, 26,34,37,42,45,50,
53,58,61)
= D' E F' + A D E' F
+ A' C D' F'

10. Definitions
Implicant: Single 1 entry or any group of 1’s that can be combined together in a K-map to form a product term.
(Dual): Single 0 entry or any group of 0’s that can be combined together in a K-map to form a sum term.
Prime Implicant: an implicant that cannot be combined with another
implicant to eliminate a term
Essential Prime Implicant: a prime implicant that contains a 1 entry
not covered by any other implicant.
Example C CD
6 Prime Implicants: AB 00 01 11 10
A' B C’ , C D, A‘ D , B C' D’ , A C , AB D' 00 1 1 01 1 1 1 B
essential 11 1 1 1 A
Minimum cover = A’ D + A C + B C ‘ D ’ 10 1 1 D

11. Definitions
Implicant: Single 1 entry or any group of 1’s that can be combined together in a K-map to form a product term.
(Dual): Single 0 entry or any group of 0’s that can be combined together in a K-map to form a sum term.
Prime Implicant: an implicant that cannot be combined with another
implicant to eliminate a term
Essential Prime Implicant: a prime implicant that contains a 1 entry
not covered by any other implicant.
Example C CD AB 00 01 11 10 00 1 1 01 1 1 1 B 11 1 1 1 A 10 1 1 D

12. Illustrating the Definitions
Prime Implicants:
B D, C D, A C, B' C
essential
Essential primes form the minimum cover
5 Prime Implicants:
B D, A B C', A C D, A' B C, A' C' D
essential
Essential implicants form minimum cover

13. Try the other axis Illustrating the Definitions Prime Implicants:CD
Prime Implicants: 00 01 11 10 AB
A D’, AB, A C, BD 00 01 1 1
essential B 11 1 1 1 1
Essential primes form the minimum cover A 10 1 1 1 D
Try the other axis
5 Prime Implicants:
B D, A B C', A C D, A' B C, A' C' D
essential
Essential implicants form minimum cover

14. Quine-McCluskey (Tabular) Method
systematically finds all prime implicants
Example: Simplify ƒ(A,B,C,D) = Sm(4,5,6,8,9,10,13) + Sd(0,7,15)
Implication Table
Column I
0000
0100
1000
0101
0110
1001
1010
0111
1101
1111
Step 1: List minterms and don’t cares using
their binary representation, and
group according to number of 1’s
Principle:
Combine terms in adjacent groups which
differ in a single variable, and eliminate the
changing variable.
Remarks:
Only terms in adjacent groups have to be
compared with one another.
Terms in non-adjacent groups differ in more
than one variable. Thus can not be combined

15. Q & M Method ƒ(A,B,C,D) = Sm(4,5,6,8,9,10,13) + Sd(0,7,15) Step 2:
Compare elements of a group with
k 1's against those with k+1 1's.
If they differ by one bit, eliminate
changing variable and place reduced
term in next column.
E.g., 0000 vs yields 0-00
0000 vs yields -000
Implication Table
Column I Column II
0000 ¦
-000
0100 ¦
1000 ¦
01-0
0101 ¦
0110 ¦
1001 ¦
1010 ¦
-101
0111 ¦
1101 ¦
1111 ¦
11-1
When a term is used in a combination,
mark that term with a check.
If cannot be combined, mark term with a star.
These are the prime implicants.

16. Q & M Method Step 2 Continues: Compare elements of a group in
Col. II with
k 1's against those with k+1 1's.
If they differ by one bit, eliminate
changing variable and place reduced
term in next column.
E.g., vs yields 01- -
-101 vs yields -1-1
Implication Table
Column I Column II Column III
0000 ¦ * *
-000 *
0100 ¦ *
1000 ¦ ¦
01-0 ¦
0101 ¦ *
0110 ¦ *
1001 ¦
1010 ¦ ¦
-101 ¦
0111 ¦ ¦
1101 ¦ *
1111 ¦ ¦
11-1 ¦

17. Q & M - Prime Implicant Chartx x x x
5,7,13,15 (-1-1)
4,5,6,7(01--)
9,13(1-01)
8,10(10-0)
8,9(10-0)
0,8(-000)
0,4(0-00)
5,7,13,15 (-1-1)
4,5,6,7(01--)
9,13(1-01)
8,10(10-0)
8,9(10-0)
0,8(-000)
0,4(0-00) x x x x x x x x x x x x x x
rows = prime implicants
columns = minterms
place an "X" if minterm is
covered by the prime implicant
If column has a single X, than the
implicant associated with that row
is essential. It must appear in
minimum cover

18. Review Gate Logic NOT AND OR Description If X = 0 then ' = 1 = 1 then
' = 0 T
ruth T
able
Switches X 1 X 1 T
rue
NOT X
False X
Description
Truth Table
Switches
Z = 1 if X and Y X Y Z
false
are both 1
AND 1
X • Y 1
true 1 1 1
X Y
Description Z
= 1 if X or Y
(or both) are 1 T
ruth T
able
Switches X 1 Y 1 Z 1
False X + Y OR T
rue X Y

19. Example : Logic circuit & its Switch realization
s = a (d+w)(c’+ e’) c e d w a s
Gate realization a e’ c’ d w 1 s
Switch realization

20. Logic Functions: NAND NAND AND
Description Z
= 1 if X
is 0 or Y T
ruth T
able
Switches X 1 Y 1 Z 1 T
rue
NAND X • Y
False X Y
Description
Truth Table
Switches
Z = 1 if X and Y X Y Z
false
AND
are both 1 1
X • Y 1
true 1 1 1
X Y
Note that switch circuit of the NAND gate is the complement
of the switch circuit for the AND gate.

21. Logic Functions: NAND, NOR, XOR, XNOR
Description Z
= 1 if both X
and Y
are 0 T
ruth T
able
Switches
NOR X 1 Y 1 Z 1 T
rue X + Y
False X Y
Description Z
= 1 if X or Y
(or both) are 1 T
ruth T
able
Switches X 1 Y 1 Z 1
False OR X + Y T
rue X Y
Note that switch circuit of the NOR gate is the complement
of the switch circuit for the OR gate.