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Motorola Mobile Devices Technology Workshop

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Presentation on theme: "Motorola Mobile Devices Technology Workshop"— Presentation transcript:

1 Motorola Mobile Devices Technology Workshop
Next-Generation Multi-Mode Baseband Modem Chipset Architecture and Implementation Brian Storm Chris LaRosa Motorola Mobile Devices Technology Workshop 4 February 2010

2 Today’s Topics Introduction Modem chipset roadmap
Architecture overview Key differentiation opportunities Cost Power consumption Modem features/capabilities Modem performance Time to market Current status / schedule

3 Introduction Wrigley/Cedar Point platform launched last quarter
Stand alone modem Scales from internal to external Application Processor 3G (WCDMA/HSPA & EGPRS) Leadership in data rate throughput Single modem spans products from: data cards to high end smart phones Many “Firsts” for Motorola 1st SAM platform 1st platform shipped with DigRF 1st platform shipped with single receiver 1st 3G platform developed with TI New DSP, peripherals, low power strategy, etc Industry isn’t standing still 3G evolution: Rel 7-HSPA+ LTE

4 What’s Next Keystone Platform is completing definition stage and design has already begun Objective Drive best in class cost Drive best in class current drain Up-rev legacy modem capabilities and add additional RAT’s Move to “Direct to Foundry” model

5 Modem Chipset Roadmap UMTS/HSPA LTE
2008 2009 2010 2011 Q108 Q208 Q308 Q408 Q109 Q209 Q309 Q409 Q110 Q210 Q310 Q410 Q111 Q211 Q311 Q411 CS SA Cedarpoint 1 Rel. 6 HSPA CS ES: 3Q ‘07 Discrete PAs SA UMTS/HSPA SA CS Gemini Cedarpoint 1.35 Rel. 7 HSPA+ Aspen LTE, HSPA+, ES: Jan’11 ES: 3Q ‘07 SA TI CPCAP ES: 3Q ‘07 ST-E CPCAP CP1.35 Wildcat ES: Jan’10 SA ES2.0: Mar‘09 Mantis CP1.25 CP1.4 ES: 2Q’11 PC SA ES: July ‘10 LCM 1.0 LTE CAT3 5, 10MHz LTE ES-1.0: 10/22/09 ES-1.0b: 11/25/09 LCM 2.0 LTE CAT3 All BW CS SA Maverick updated to reflect CP1.5 -> CP1.35 (1Q earlier) & CP1.4 (1Q later) split, current dates projected Removed Smarti UEMicro from plans First commercialization of Keystone will be with LU or AnacondaLTE Smarti-LU pulled in from Feb’10 (ES) to Nov’09 (ES-1.3) TDD removed from initial LCM2.0 delivery plans Maverick ES-1.3: Nov‘09 ES-2.0: Jul ‘10

6 Keystone Targeted Configurations/Modes
Priority Keystone AP/Modem Handset Platform 1. Multi-mode modem. To allow for efficient system implementation with AP 2. Data Card products and support for differentiating data card applications. (MiFi, Sideshow..) Supporting enhanced data card features 3. enable potential to support low tier stand alone handset configuration 1. Keystone Data Card Platform 2. Keystone Standalone Handset Platform 3.

7 Aspen Block Diagram

8 Modem Cores Shared Application Cores
Processors & Memory Modem Cores 400MHz ARM Baseband Processor 32KB L1 Data Cache 32KB L1 Instruction Cache 96KB TCM (unified, interleaved) 3x 32KB (1x TCM-A. 2x TCM-B) 128KB L2 Cache 400MHz Modem DSP 256KB L1 RAM (Program & Data total) Shared 400MHz Audio/Multimedia Processor 32KB L1 Instruction Cache 128KB L1 RAM (Data) 256KB Local RAM 512KB Local ROM Shared/Internal L3 Memory 64KB L3 RAM 384KB L3 ROM Highly Efficient External Memory Interface Support for 200MHz LPDDR2 SDRAM & NVM Support for 166MHz (mandatory) NOR Interface Support for JC64 MMC NAND flash interface Chip-to-Chip (C2C) Interface Shared Memory Interface for sharing SDRAM with AP (SMI) Debug Standard Real Time Trace interface (ETM on ARM) SW bypass able HW acceleration (where MCPS requirement allows) Efficient SW Data logging support Profiling Counter Subsystem SDIO Host eMMC SD Card Application Cores 600MHz ARM Application Processor 32KB L1 Data Cache 32KB L1 Instruction Cache 256KB L2 Cache

9 Modem Subsystem Modem HW Acceleration Motorola Peripheral IP
WCDMA/HSPA GSM EDGE Symbol Processor (GESP) LTE (iDEN modem shares 2G DSM & L1T but no other HWA required) Motorola Peripheral IP Air Interface Timers (L1T) Deep Sleep Controllers Multi-channel Linked-List Modem DMA with Data Manipulation & Ciphering capability (tightly coupled) GEA1/2/3, A5/1/3 UIA1/UEA1 (Kasumi, f8/f9) 128-EIA1/128-EEA1 (SNOW3G) 128-EIA2/128-EEA2 (AES in CTR and CMAC modes) RF Interfaces DigRF 3G with multiplexed diversity support DigRF V4 with dual Rx lane and multiplexed diversity support SSI/SPI interface for iDEN Concurrent operation supported for Dual Radio configurations (e.g. iDEN & LTE for simultaneous voice & data) Chip-to-Chip (C2C) Interface Co-Processor Interface to support external companion modems (M2MI)

10 Apps Subsystem Multimedia Support Connectivity
3MP Camera support (Image/Video Stabilization, Digital Zoom) QVGA Display support (24-bit color) MPEG4 CIF 30fps 768kbps (decode) H264 CIF 30 fps 1024kbps (decode) VC-1 QVGA 30 fps 768kbps (decode) Connectivity GPS Bluetooth WLAN 802.11b/g 802.11n 1x GHz Multi-channel Linked-List System DMA with Data Manipulation Security SHA-256 Hashing Engine AES Cryptographic Engine Random Number Generator Integrated Efuse or Non-Volatile Memory for secure key storage Universal Serial Bus HS-USB Slave w/ integrated USB-PHY (common descriptor interface, LTE DMA front-end) HS-USB Host (host interface for companion modem) FS-USB Host

11 Best in Class Cost Remove Cost from IC Development Effort
Single Multi-RAT devices Shared development cost across multiple RAT’s Smaller geometries are making the cost adder of unused silicon less & less of an issue. Eliminating larger margins of major design house more than offsets silicon adder Reduce piece part cost Move aggressively to the next process node Choice of foundry partners under our control in direct to foundry model Direct to foundry model eliminates the margins added by the middle man Reduce Product Development Cost (HW & SW) Multiple generations with common architectures & cores New generations are evolutions, not revolutions Keep AP & Modem domains independent and scalable

12 Best in Class Current drain (1 of 2)
Smarter DVFS strategy Multi-processor distributed processing Improved Processor efficiency

13 Best in Class Current drain (2 of 2)
Smarter Power Domain strategy

14 Aspen Modem Features/Capabilities: Current PoR
2G GSM, GPRS, EDGE 3G WCDMA, HSPA+ 4G LTE GPRS/EDGE Class 12 5 slots: 4 RX / 1 TX DTM Class 9 GERAN Rel-8 2G/LTE interworking EDGE Advanced Receiver Hybrid LSIC Increased HW Acceleration GESP Lite + GESP Demod Under Investigation: Rx Diversity (MSRD) GPRS/EDGE Classes 30-34 6 slots: 5 RX / 1 TX 3GPP Rel-7 All Mandatory Features HSDPA Cat 14: 21 Mbps DL HSUPA Cat 7: 11.5 Mbps UL Rel-7 Features: 64-QAM DL, 16-QAM UL DRX / DTX, Enhanced L2, Enhanced FDPCH HSDPA Advanced Receiver Types 2, 3, 3i Joint-MMSE Equalizer 3GPP Rel-8 FDD (Full Duplex) UE Cat 3 100 Mbps DL 50 Mbps UL BW: 1.4, 3, 5, 10, 15, 20 MHz All DL Transmission Modes SIMO Tx Diversity 2x2 MIMO 4x2 MIMO MIMO Advanced Receiver ML-SIC

15 Aspen Modem Capabilities: Peak Data Rates (Mbps)
Increased BW: 5  20 MHz Two-Layer MIMO 16QAM 64QAM Increased BW: 0.2  5 MHz Higher Order Modulation 16QAM 64QAM

16 Techniques for Improving Physical Layer Performance
Voice Call Performance Dropped call rate Data Call Performance Latency Peak user throughput Average user throughput Average spectral efficiency (bps/Hz) Key performance indicators Technique Peak User T-Put Average User T-Put / Spectral Efficiency Increased User Bandwidth High-Order Modulation (16-QAM, 64-QAM) MIMO (Multi-Input Multi-Output) Hybrid ARQ (HARQ) Adaptive Modulation and Coding (AMC) Frequency Selective Scheduling (FSS) Receive Diversity Advanced Receiver Techniques Opportunity for UE differentiation

17 2G (GSM/GPRS/EDGE) Advanced Receiver Evolution
Modulation Type Legacy Solution (Cedar Point) Planned Upgrade (Aspen) Potential Improvement GMSK DARP AR10 2X 1-pass No Rx Div support DARP AR10 2X 2-pass Up to 2 dB 8-PSK DFE-MMSE with RSSE 4 states Lindoff DC removal Hybrid LSIC Short channels: SP LSIC Long channels: legacy equalizer Up to 6 dB DARP: Downlink Advanced Receiver (AR) Performance DFE: Decision Feedback Equalizer Rx Div: Receive Diversity MMSE: Minimum Mean-Squared Error SP: Single-Port LSIC: Least-Squares Interference Cancellation Source: GSM DSP SW team (Toulouse) See backup slides for additional information

18 Generation/Capability Rx Div + Joint Equalization
3G (HSDPA) Advanced Receiver Evolution + 64-QAM 15-code HSDPA 21.5 Mbps Generation/Capability 10.1 Mbps 5-code HSDPA 384 kbps 3.6 Mbps Release 99 WCDMA Release 5 HSDPA Release 6 HSDPA / HSUPA Release 7 HSPA+ Motorola Modem IC's WCSP / POG WAMMO1 / ArgonLV WAMMO3 / Cedar Point WAMMO4 / Aspen Advanced Receivers SCH IC + Equalization Rx Div + Joint Equalization Improved Estimation RAKE Dual-LMS J-MMSE Enhanced J-MMSE

19 3G Advanced Rx Performance Compliance
3GPP Receiver Types (HSDPA) Rx Type Reference Receiver 3GPP Spec Release "0" Rake 5 1 Rx Diversity (Rake) 6 2 LMMSE 3 Rx Diversity & LMMSE 7 3i Rx Diversity & LMMSE with Multiple Base Cancellation 3GPP HSDPA Receiver Type IC (WAMMO Version) 3GPP Release WAMMO HSDPA Receiver Components 1 2 3 3i Rake Rx Diversity Equalizer Rel-5 Rel-6 Rel-7 ArgonLV (WAMMO1) Yes Dual-LMS SKYE (WAMMO2) Enhanced Dual-LMS Cedar Point (WAMMO3) Joint MMSE with IC Aspen (WAMMO4) Enhanced J-MMSE* Fully compliant Partial compliance Not compliant * Improved equalizer training using available control channels (PCCPCH, HS-SCCH)

20 WAMMO3 (Cedar Point) J-MMSE Equalizer
w = R-1p R = Autocorrelation matrix p = Channel estimation vector Matrix Assembly / Equation Solver Expanded and upgraded in WAMMO4 (Aspen) Statistics Engine: Produce autocorrelation (R) and channel estimate (p) statistics in hardware Block FIR Filter: Produces moving average of block statistics from statistics engine Matrix Assembly: Construct and scale normal equations Rw=p Conjugate Gradient (CG) Solver: Solve normal equations to produce w Data LTF (linear transversal filter): Filter RXIQ at chip-rate with w to produce equalized stream

21 3G (HSPDA) Advanced Receiver Performance
IC Adv Rx ArgonLV WAMMO1 Skye WAMMO2 Cedar Point WAMMO3 Aspen WAMMO4

22 3G (HSPDA) Advanced Receiver: Performance Data
Lab Data (3GSM DSP Team) Simulation Data ~2.0 dB Gain ~1.5 dB Gain Lab measurements show significant gains (1.5 to 2 dB) vs. a Sierra data card with a Q-COMM chipset, particularly with increasing vehicular speed The WAMMO3 Type 3i receiver is expected to yield a gain of ~1.5 dB vs. a conventional Type 3 receiver at low geometries

23 LTE Core Modem Block Diagram
Key Performance Differentiators

24 LTE Channel Estimation
Reference (pilot) symbols are transmitted at selected positions in time and frequency.  2D interpolation/filtering is performed by interpolating first in the frequency direction, then in the time direction

25 LTE Core Receiver Implementation Dual-Engine to Support Multiple Downlink Transmission Modes
Channel Estimates LLR’s to FEC Decoder FFT Output Samples MRC used for demodulation of transmissions not using spatial multiplexing Noise Estimates ML-SIC used for demodulation of transmissions using spatial multiplexing MRC = Maximal Ratio Combining ML-SIC = Maximum Likelihood estimation with Successive Interference Cancellation

26 ML-SIC Reception and Link Adaptation Algorithmic View

27 Key MLE Simplification #1: QR Decomposition w/ Resource Sharing
Extensive time-sharing of multipliers to minimize cost/complexity (9 multipliers running at 4*fs)

28 Key MLE Simplification #2: Distance Calculation
MLE must compute the distance from z0 to all constellation points Euclidean distance can be approximated by Manhattan distance with minimal performance degradation Euclidean distance: Manhattan distance approximation:

29 LTE 2x2 MIMO Receiver Performance Comparison
Low Spectral Efficiency High Spectral Efficiency Receiver Performance Rankings ML: Maximum-Likelihood estimation MMSE: Minimum Mean Squared Error Estimation SIC: Successive Interference Cancellation ML-SIC MMSE-SIC MMSE Low Spectral Efficiency 1 3 High Spectral Efficiency 2

30 Simulated LTE Link Performance: 2x2 MIMO
Improved SIC feedback mechanism in LCM2

31 Aligning Simulation Results with Lab Measurements
Excellent alignment between lab measurements and simulations

32 Baseband Modem Hardware (HDL) Development Methodology
Standards Definition 3GPP Specifications Algorithm definitions Floating-point reference models Link performance results Algorithm Definition Architecture & Requirements Definition Hardware/software partitioning Block diagrams Interface definitions Sub-system requirements Feedback based on implementation impacts Reference Model Development HDL (RTL) Implementation Bit-accurate reference models Test vectors + expected outputs Performance characterization / optimization Synthesize-able HDL model (VHDL, Verilog) FPGA-ready ASIC-ready

33 Modem Simulation and Verification Methodology
System Simulation Model Multiple UE’s deployed in cellular system Sector T-Put / Spectral Efficiency User T-Put (Average & Cell Edge) Latency, Fairness, etc. Link Error Prediction (LEP) Mapping Used during 3GPP standardization Link Simulation Model Bit-accurate model of UE implementation within full downlink simulation Frame Erasure Rate (FER) User T-Put RAN4 Performance Reqs UE Receiver Reference Model Used to characterize and optimize link-level performance of actual UE implementation eNode-B Transmitter Model Mobile Channel Model Link Performance Analysis Test vectors used for verification of UE implementation (stimuli + expected results) HDL simulations used to validate that implementation matches reference model HDL Implementation Model

34 Modem Pre-Silicon Verification Methodology
Link Simulation Pre-silicon verification: Link simulations of reference model HDL (RTL) simulations to match implementation against reference model FPGA verification Test vectors (baseband) Commercial test equipment (baseband) Commercial test equipment (RF) Lab testing with eNode-B Field testing, IODT, etc. ASIC verification (pre-silicon) Gate-level simulations Formal verification Static timing analysis Vectors Bit-Accurate Reference Model HDL (RTL) Simulation HDL Implementation Model Brassboard “Brick”

35 Current Status / Schedule
65nm 40nm Cedar Point Aspen 2G/3G/4G Multimode Rel-7 HSPA+ 21 Mbps DL, 11.5 Mbps UL Rel-8 LTE 100 Mbps DL, 50 Mbps UL 2G / 3G 3GPP Rel-6 HSPA 10.1 Mbps DL / 5.76 Mbps UL New IP and HW Acceleration Modem Feature Upgrades Modem Performance Upgrades Power Management Upgrades Technology Shrink 65nm 65nm LCM1 LCM2 3GPP Rel-8 LTE BW: 5, 10 MHz 50 Mbps DL / 25 Mbps UL Limited Feature Set 3GPP Rel-8 LTE (Full Compliance) BW: 1.4, 3, 5, 10, 15, 20 MHz 100 Mbps DL / 50 Mbps UL Power Management Upgrades Radio Performance Upgrades LTE Data Card LCM1 LCM1: Samples received Oct 2009; currently integrated into data card LCM2: Samples expected mid 2010 Aspen: Samples expected early 2011

36 Brian Storm, Chris LaRosa
Technology Workshop “Next-Generation Multi-Mode Baseband Modem Chipset Architecture and Implementation” Brian Storm, Chris LaRosa Panel Discussion: Rob Bero, Michael Eckert, Manash Goswami, Armin Klomsdorf

37 Backup Slides

38 Block diagram – DARP AR10 2-pass GMSK equalizer
Evolution of current CP1.x DARP AR10 1-pass algorithm Floating implementation on GESP-Demod HWA will allow more accuracy in computations

39 Block diagram – LSIC Single Port 8-PSK equalizer
This only describes the LSIC equalizer. Hybrid LSIC solution will use Legacy DFE-RSSE for long channels. Source: TO team

40 GMSK Performance Simulations Results – DARP AR10 2-pass
Performance improvement (dB) between legacy GMSK equalizer (DARP AR10 1-pass) and evolution targeted on Aspen (DARP AR10 2-pass) Simulations results more than 0.5 dB improvement

41 EDGE MCS5-9 Performance Simulations Results – Hybrid LSIC
Values indicated are Eb/N0 or C/Ic (in dB) to reach spec - 10% or 30% Data BLER

42 EDGE MCS5-9 Performance Simulations Results – Hybrid LSIC
Values indicated are C/Ia (in dB) to reach spec - 10% or 30% Data BLER


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