1. Use of Data Analysis and TCAD Simulations to Understand the Characteristics and Reliability of High Voltage MOS Transistors Jone F. Chen Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, Tainan, Taiwan

2. 2 Purpose High voltage metal-oxide-semiconductor (MOS) transistors are widely used in smart power management integrated circuits (IC), liquid-crystal display (LCD) drivers, and NAND flash memory periphery circuitry because of the compatibility to be integrated into standard complementary metal-oxide- semiconductor (CMOS) process. Since high voltage MOS transistors are operated under high voltage, breakdown voltage (V BD ) is a critical device parameter and hot-carrier induced device degradation is an important reliability concern. This work reports analysis of V BD and hot-carrier induced device degradation in high voltage MOS transistors with varied process in drift region.

3. 3 Outline Off-state Breakdown Hot-carrier Induced Degradation TCAD Simulations Device Description Results and Discussions Conclusions

4. 4 Off-state Breakdown High E-field in the junction causes electron/hole pair generation. This avalanche multiplication results in breakdown.

5. 5 Hot-carrier Induced Degradation Carriers accelerate in high E-field region and gain sufficient energy to create damage in gate oxide or oxide/Si interface, degrading device characteristics.

6. 6 Hot-carrier Stress Procedure Stressing were carried out at high drain voltage and interrupted periodically to measure I D degradation.

7. 7 Technology Computer-Aided Design (TCAD) Simulations ATHENA DeckBuild Structure File Command File ATLAS Device Simulator Solution Files Log Files Runtime Output TonyPlot Visualization Tool About TCAD TCAD combines two kinds of tools: Core tools in charge of running different parts of simulations. Interactive tools are which users manage their settings.

8. 8 Device Description High voltage MOS transistors were fabricated by an advanced CMOS compatible process. The length of gate and N - drift region are 2  m and 1.2  m, respectively. Four devices (A, B, C, D) were fabricated. A is the control device. B, C, D are implanted with BF 2 with low, medium, and high doping levels in N - drift region.

9. 9 Net Doping Device D has less net doping due to BF 2 implant in drift region. AD

10. 10 V BD Results Device D has the highest V BD. Higher BF 2 implant dosage results in higher V BD.

11. 11 V BD Analysis TCAD simulations suggest that higher V BD in device D is due to the absence of high E-field in drift region. AD

12. 12 Hot-carrier Stress Results Device D has the greatest I D degradation. Higher BF 2 implant dosage results in higher I D degradation.

13. 13 Hot-carrier Stress Analysis TCAD simulations show that the current-flow path in device D is closer to Si-SiO 2 interface. The effect of hot- carrier induced damage on I D degradation is greater, leading to enhanced I D degradation in device D. AD

14. 14 Conclusions BF 2 implant in drift region of high voltage MOS transistors results in higher V BD. BF 2 implant in drift region of high voltage MOS transistors enhances hot-carrier induced device degradation. Care should be taken in determining drift region process because a trade-off between V BD and hot-carrier induced device degradation is observed.

15. Thank you for your Attention