1. CSE 141Dean Tullsen Designing a Pipelined CPU

2. CSE 141Dean Tullsen Quiz next Wednesday (2/20) No class on Monday 2/18 Quiz will be full hour (less time pressure?) How do you set control lines? What would happen if some line was stuck on (or off) How would you add such-and-such instruction Why is such-and-such needed Where do you insert no-ops or stalls to execute...

3. CSE 141Dean Tullsen Review -- Single Cycle CPU

4. CSE 141Dean Tullsen Review -- Multiple Cycle CPU

5. CSE 141Dean Tullsen Review -- Instruction Latencies Cycle 1Cycle 2Cycle 3Cycle 4Cycle 5 IfetchReg/DecExecMemWrLoad IfetchReg/DecExecMemWrLoad Single-Cycle CPU Multiple Cycle CPU IfetchReg/DecExecWrAdd

6. CSE 141Dean Tullsen A Pipelined Datapath IF: Instruction fetch ID: Instruction decode and register fetch EX: Execution and effective address calculation MEM: Memory access WB: Write back

7. Pipelined Datapath Warning – “write register” line is incorrect in this figure!

8. CSE 141Dean Tullsen Execution in a Pipelined Datapath CC1CC2CC3CC4CC5CC6CC7CC8CC9 lwlw lwlw lwlw lwlw lwlw steady state steady state IFIDEXMEMWB IMReg ALU DMReg IFIDEXMEMWB IMReg ALU DMReg IFIDEXMEMWB IMReg ALU DMReg IFIDEXMEMWB IMReg ALU DMReg IFIDEXMEMWB IMReg ALU DMReg

9. CSE 141Dean Tullsen Instruction Latencies and Throughput Single-Cycle CPU Multiple Cycle CPU Pipelined CPU Cycle 1Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8 IFDecEXMemWBLoad IFDecEXMemWBLoad IFDecEXMemWBLoad IFDecEXMemWBLoad Cycle 1Cycle 2Cycle 3Cycle 4Cycle 5 IFDecEXMemWBLoad IFDecEXMemWB Load

10. CSE 141Dean Tullsen Pipelining Advantages Higher maximum throughput Higher utilization of CPU resources But, more hardware needed, perhaps complex control

11. CSE 141Dean Tullsen Mixed Instructions in the Pipeline IMReg ALU Reg IMReg ALU DMReg CC1CC2CC3CC4CC5CC6 lwlw add

12. CSE 141Dean Tullsen Pipeline Principles All instructions that share a pipeline must have the same stages in the same order. –therefore, add does nothing during Mem stage –sw does nothing during WB stage All intermediate values must be latched each cycle. There is no functional block reuse – example: we need 2 adders and ALU (like in single-cycle) IMReg ALU DMReg IF IDEXMEM WB

13. CSE 141Dean Tullsen Pipelined Datapath Instruction FetchInstruction Decode/ Register Fetch Execute/ Address Calculation Memory AccessWrite Back registers!

14. CSE 141Dean Tullsen The Pipeline in Execution add $10, $1, $2 Instruction Decode/ Register Fetch Execute/ Address Calculation Memory AccessWrite Back

15. CSE 141Dean Tullsen The Pipeline in Execution lw $12, 1000($4)add $10, $1, $2 Execute/ Address Calculation Memory AccessWrite Back

16. CSE 141Dean Tullsen The Pipeline in Execution sub $15, $4, $1lw $12, 1000($4)add $10, $1, $2 Memory AccessWrite Back

17. CSE 141Dean Tullsen The Pipeline in Execution Instruction Fetch sub $15, $4, $1lw $12, 1000($4)add $10, $1, $2 Write Back

18. CSE 141Dean Tullsen The Pipeline in Execution Instruction FetchInstruction Decode/ Register Fetch sub $15, $4, $1lw $12, 1000($4)add $10, $1, $2

19. CSE 141Dean Tullsen The Pipeline in Execution Instruction FetchInstruction Decode/ Register Fetch Execute/ Address Calculation sub $15, $4, $1lw $12, 1000($4)

20. The Pipeline in Execution, with controls (This figure has correct Write register bus)

21. CSE 141Dean Tullsen Pipelined Control FSM isn’t really appropriate Combinational Logic (like single-cycle design)! –signals generated once in ID stage –follow instruction through the pipeline –get used in whatever stage they are needed IF/IDID/EXEX/MEMMEM/WB control instruction

22. CSE 141Dean Tullsen Pipelined Control Signals

23. CSE 141Dean Tullsen The Pipeline with Control Logic

24. CSE 141Dean Tullsen Is it really that easy? Suppose initially, register i holds the number 2i What happens when... add $3, $10, $11 - this should add 20 + 22, putting result 42 into r3 lw $8, 50($3) - this should load r8 from memory location 42+50 = 92 sub $11, $8, $7 - this should subtract 14 from that just-loaded value

25. CSE 141Dean Tullsen The Pipeline in Execution lw $8, 50($3) add $3, $10, $11Execute/ Address Calculation Memory AccessWrite Back 20 22

26. CSE 141Dean Tullsen The Pipeline in Execution sub $11, $8, $7lw $8, 50($3)add $3, $10, $11Memory AccessWrite Back 20 22 42 6 16 50 Ooops! This should have been “42”! But register 3 didn’t get updated yet.

27. CSE 141Dean Tullsen The Pipeline in Execution add $10, $1, $2sub $11, $8, $7lw $8, 50($3)add $3, $10, $11Write Back 6 50 16 14 56 And this should be value from memory (which hasn’t even been loaded yet). Recall: this should have been “92” 42

28. CSE 141Dean Tullsen Data Hazards When a result is needed in the pipeline before it is available, a “data hazard” occurs. IMReg ALU DMReg IMReg ALU DM IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) R2 Available R2 Needed