1. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC R&D work on gigabit optical link for ATLAS ID readout upgrade at SMU Objectives: 1.Evaluate the GOL chip in an optical link system and perform characteristic measurements (jitter, bit error rate, etc). (done in 2006) 2.Irradiate the GOL up to 100 Mrad and measure SEE, TID. (done in Jan./Feb.2007) 3.Continue evaluation on link components in radiation : VCSELs, fibers (in progress in 2007) 4.Work with LBNL and UCSC to develop a 1.6 gigabit optical link to readout the test stave. (in progress in 2007) 5.Participating in the development of a baseline optical link for the ID readout upgrade. Work with groups developing ABCNext, LOC, GBT and the Versatile link (module). (in progress for 2007 – 2009). Manpower: One FTE in a team of three FTEs, two RAs and two faculty members.

2. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Test results on the GOL in 2006 – 2007(1) 1.The test system designed and constructed for in-lab and irradiation tests: 32 bits/40 MHz 16 bits/80 MHz A big board for a small chip: For in-lab (BER, jitter and power- up schemes) and irradiation (gamma, proton and neutron) tests. The VCSEL is mounted 2 mm away from the GOL. The LC connector is 4×4 mm2 cross, and 50 mm boot length. The fiber is 1.6 mm OD. GOL: 13×13mm2×1.7mm, ~400 mW. The actual PCB space needed for in the actual application will be less than 20 mm × 30 mm (the red mark). The upper 3U crate hosts boards in the beam (gamma or proton). The lower 6U crate hosts controlling and DAQ boards. The master PC can be placed 40 meters away, connecting with USB. LabVIEW based GUI.

3. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Test results on the GOL in 2006 – 2007 (2) 2.In-lab characterization tests on the GOL: oBit Error Rate (BER): T r -225ps, T f -245ps. Eye mask test. oPower-up schemes studied and found to be reliable. oThe jitter tests: GOL reference clock jitter transfer function: Clock jitter cutoff at about 1 MHz. Complies with the adapted IEEE standards. Low frequency jitter (noise) source at the system level needs to be watched for. GOL-TLK optical link jitter tolerance: Jitter tolerance complies with the IEEE standard. This plot specifies the transmitter reference clock jitter to be below the blue line to achieve a BER less than 10 -12. BER > 10 -12 BER < 10 -12

4. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Test results on the GOL in 2006 – 2007 (3) 3.Irradiation tests on GOL: oSource: 230 MeV proton. oTests: TID up to 106 Mrad (Si); SEE cross section (probability). oResults: TID: No supply current increase during the irradiation. GOL functions error free immediately after the beam is off, very small change in eye diagram and jitter.  survives the TID test of 106 Mrad(Si) SEE:  very small SEE cross section. Flux (protons/cm 2 /s) Fluence (protons/cm 2 ) Dose (Mrad(Si)) SEU events LoL Bit Error Cross-section (cm 2 ) LoL Bit Error < 6 x 10 8 1 x 10 11 5 x 10 -3 0 < 2.7 x 10 -11 1 x 10 9 3.7 x 10 12 0.21 02.7 x 10 -13 <2.7 x 10 -13 2 x 10 10 7.6 x 10 13 417 42.2 x 10 -13 5.3 x 10 -14 5 x 10 11 1.9 x 10 15 100200 201.1 x 10 -13 1.1 x 10 -14 Eye diagram: before (left) and after Before irradiationAfter irradiation Jitter ComponentsTx clkSerial DataTx clkSerial Data Random (RMS)10.2ps4.6ps11.1ps4.7ps Deterministic (Pk-Pk)67.6ps55.6ps67.0ps57.9ps Total@BER-14196.1ps106.7ps211.7ps111.8ps

5. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Test results on VCSEL and fiber in 2006 – 2007 4.Tests on fiber and VCSEL. The Fiber: oInfinicor SX+ 50/250  m/1.6mm MM 10G fiber from Corning. Germanium doped. oTested wit Gamma (Co-60) and Proton (230 MeV, 1.9×10 13 proton/cm 2 ). oVery small light loss at low flux (dose rate). Big loss at high flux but anneals very quickly (within 1 hour) back. oVery promising for LHC upgrade. oMore tests with gamma needed. The VCSEL: oTwo HFE6192-562 (10G LC w/ 50 ohm flex) from Finisar tested. oIrradiated with 230 MeV proton, 1.9×10 13 proton/cm 2. oThe VCSELs are biased during irradiations. oEye diagram – see plots and table. oLooks very promising but more tests needed. VCSEL Before irradiationAfter irradiation Rise/fall time (ps) O-power (  W) Rise/fall time (ps) O-power (  W) L1114/130431110/128133 L2120/132450122/132295 L1, before irradiation L1, after irradiation

6. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Conclusions on the GOL, VCSEL and fiber evaluation 1.GOL complies with the adapted (to 1.6 Gbps) IEEE standard for Gigabit Ethernet (1.25 Gbps). 2.GOL is tested to be rad-resistant up to 106 Mrad (Si). 3.The SEE probability is measured to be 1.1×10 -13 for link frame loss and 1.1×10 -14 for single bit flip.  The GOL chip is a good candidate for 1.6 Gbps optical link, rad- hard to the ID requirement. 4.We have preliminary candidates for the VCSEL and the fiber.

7. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Plans for 2007 and 2008 1.Issues on a gigabit optical link architecture: oRad-hard serializer + TOSA (driver, VCSEL), oRad-hard fiber, oReference clock jitter control (cleaning), oInput data bit-to-bit skew control, oReliability and single point failure prevention. 2.To address the above issues, we plan to: oCollaborate with LBNL and UCSC to construct a GOL based prototype link to readout the test stave. To study gigabit link system issues with the ABCNext (ABCD for now) upstream electronics, with the QPLL clock jitter cleaner. A dual link system will be investigated to address The single point failure, The SEE CERN QPLL chip will be used as the clock cleaner. oDo more irradiation tests on fiber and VCSEL to identify candidates for a multi-gigabit optical link for SLHC ID readout upgrade. oCarry out reliability tests on the GOL, TOSA to provide info about the redundancy in the link. oInvestigate the LOC and the GBT as the serializer chip when they become available for higher bandwidth link.

8. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Our design of the GOL based prototype optical link (1) connectorLVDS  CMOS Delay line + QPLL GOL TOSA VCSEL fiber data (32) clock Control logic The transmitter board. The output can be chosen to go through TOSA (CERN rad-hard versatile link) or a VCSEL to avoid failures in the optical device and fiber. The delay line in the data bus is used to address the bit-to-bit skew problem. In ABCnext, this delay will be implememented. Delay lines

9. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Our design of the GOL based prototype optical link (2) fiber ROSA PIN+TIA+LA TLK 2500 connectorCMOS  LVDS1:2 deMUX data (32) clock The receiver board

10. J.Ye @ SMU Report: R&D work for ID upgrade May 3, 2007 @ UCSC Budget (for 2008) manpowerOne FTE @ $55k/yr, w/ 25% benefit$68.75k M&SPCB fab. + assembly + components$10k TravelFor gamma irradiation tests only$5k OthersReliability test$0 TotalWith SMU 45.5% overhead$121.85k