2. Combinational Logic Design
Design using SSI chips
Arithmetic Circuits
Code Convertor

3. Combinational Logic Circuits
The term "combinational" comes to us from mathematics which means an unordered set where nobody cares which order the items came in
With combinational logic, the circuit always produces the same output solely by a given set of inputs , regardless of the order the inputs are changed
If there are m outputs and n inputs then there are m Boolean functions, one describing each outputs
The inside of a combinational circuit is made of logic gates and it does not store any information (i.e. memoryless)
There are circuits which depend on inputs and previous outputs. These circuits are called sequential logic where we will discuss in later chapter
Combinational logic circuits are important components of digital systems

4. Combinational vs. Sequential Logic
(a) Combinational (b) Sequential
Output = F (In) Output = F (In, Previous In)

5. Designing Combinational Circuits
In general we have to do following steps:
From the specifications of the circuit, determine the required number of inputs and outputs and assign a letter symbol to each
Derive the truth table that defines the relationship between inputs and outputs
Obtain the simplified Boolean functions for each output as a function of the input variables
Draw the logic diagram
Verify the correctness of the design

6. Arithmetic Circuits
Arithmetic circuits are the ones which perform arithmetic calculations on binary numbers like addition, subtraction, multiplication, and division etc.
Arithmetic circuits can be built using logic circuits and they are excellent examples of combinational logic design
We will build arithmetic circuits by using the design procedure as stated previously

7. Adder Adders are the basic building blocks of all arithmetic circuits
Adders add two binary numbers and give out sum and carry as output
In modern computers adders reside in the arithmetic and logic unit (ALU) where other operations are performed
Basically we have two types of adders
Half Adder
Full Adder

8. Half Adder X 1 Y S C-out Half Adder Truth Table S(X,Y) = S (1,2)
Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit
This operation is called half addition and the circuit to realize it is called a half adder X 1 Y S
C-out
Half Adder Truth Table
Inputs
Outputs
S(X,Y) = S (1,2)
S = X  Y
C-out(X,Y) = S (3)
C-out = XY X Y
Sum S
Half
Adder X Y S
C-OUT
C-out

9. Full Adder
Sum S
C-in X 1 Y XY 2 3 6 7 4 5
Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit
The S function is the three-bit XOR function (Odd Function): S = X  Y  (C-in)
C-in X 1 Y XY 2 3 6 7 4 5
Carry C-out
C-out = XY + X(C-in) + Y(C-in)

10. Full Adder Circuit using XOR and Basic Gates
Logical Implementation

11. Full Adder implemented by Two Half Adders and an OR Gate
A ‘Full Adder’ can also be implemented using two half adders and an ‘OR’ Gate as follows:
The sum S = X  Y  (C-in)
The carry out

12. Full Adder implemented by Two Half Adders and an OR Gate (Cont.)
Therefore and
Block diagram representation of a full adder using two half adders

13. Adding Two Binary Numbers
We want to add two 4-bit binary numbers
We use a series of half and full adders
Since there is no carry into the first stage, we can use a half adder there
For each other stage we use a full adder and just carry in from the previous stage
The carry out at the end indicates that the sum is too large to be represented by 4 bits

14. Subtraction If we want to do subtraction, the circuit is very similar
Looking at the truth table for
A - B
The only difference between a half adder and a half subtractor is the borrow
In order to perform this subtraction a digit has to be borrowed from the next highest column of the subtraction
When it borrows, it gets a 2 and the operation then becomes = 1
The Borrow output is set to indicate that borrow operation is required

15. Half Subtractor Symbol
Subtracting a single-bit binary value Y from anther X (i.e. X - Y) produces a difference bit D and a borrow out bit B-out
This operation is called half subtraction and the circuit to realize it is called a half subtractor
D(X,Y) =  (1,2)
= X'Y + XY'
Thus, D = X  Y
B-out(X,Y) =  (1)
Thus, B-out = X'Y
Symbol

16. Half Subtractor circuit
Again, we shall represent the half subtractor using a box
Since the two inputs of a subtractor are different, we indicate the subtrahend with a ‘-’

17. Full Subtrator
Subtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit
This is called full subtraction
D = X Å Y Å (B-in)
Note: D= X – Y – B-in
B-out = X'Y + X'(B-in) + Y(B-in)
= X'Y + B-in(X  Y)'
(In the same way as we did with the full adder)
D(X,Y, B-in) = S (1,2,4,7)
B-out(x, y, B-in) = S (1,2,3,7)

18. Full Subtractor Circuit Implementation
X-OR gate implementation
of half subtactor
Full subtractor using two half subtractors and an OR gate

19. Parallel Adder IC As shown in the pin layout diagram, the IC 7483
Accepts two 4-digit numbers A4A3A2A1, B4B3B2B1 and a carry-in Ci as inputs
Produces a 4-digit sum output 4321and a carry-out Co
If the SUM of the two inputs plus the carry-in is between 0 and 15, the SUM appears in the  outputs and the carry-out is '0‘
If the SUM is between 16 and 31, carry-out C0 becomes ‘1‘ and the  outputs are 16 less than the SUM
Example (not using 2’s complement)
A4A3A2A1 = 0111, B4B3B2B1 = 1010, Ci = 1
So, result should be (18)
As expected, the ICs produces
Co = 1 and 

20. Cascading the ICs
A IC only accept 4-bits Boolean variables at its input
So, how to do addition which involve 5-bits or more
Find another suitable IC! Or, by cascading ICs
To add two 8 bit numbers X8X7X6X5X4X3X2X1 and Y8Y7Y6Y5Y4Y3Y2Y1 , connect two as below
X8X7X6X5
X4X3X2X1
Y8Y7Y6Y5
Y4Y3Y2Y1
2nd stage
produce MSB
1st stage
produce LSB

21. n-bit Subtractors
An n-bit subtracor used to subtract an n-bit number Y from another n-bit number X (i.e. X - Y) can be built by using an n-bit adder and n inverters:
Find two’s complement (1's complement plus 1) of Y by: Inverting all the bits of Y using the n inverters
Adding 1 by setting the carry in of the least significant position to 1
The original subtraction (X - Y) now becomes an addition of X to two’s complement of Y using the n-bit adder

22. 4-bit Subtractor using 4-bit Adder

23. Adding and Subtracting
Since the circuits are so similar, it is reasonably easy to combine them together into a single circuit, with a control line used to select either addition or subtraction
The only difference between the half adder and the half subtractor is the NOT
The above table gives a truth table of what we require
What logic gate can fulfill this truth table?

24. Adding a Control Line
If we define a 0 on our control signal to mean Add then the input to the AND Gate should be the same as our A signal
When the control signal is 1, we want to do a subtraction, so we require the input to the AND Gate to be the NOT A signal
We make our full adder/subtractor just as before, with all the control inputs tied together

25. Adder and Subtractor Using 74283 IC
When the switch is closed, is an adder
A '0' is applied to Ci and the EX-OR gates
So, there is no Carry-in and
Addend pass through the EX-OR unchanged (1  0 = 1, 0  0 = 0)
When the switch is opened, becomes a subtractor
A ‘1' is applied to Ci and the EX-OR gates
So, there is a Carry-in (adding 1) and
Addend pass through the EX-OR inverted (1  1 = 0, 0  1 = 1)
So, acts as an subtractor, by adding (2’s complement of Y4Y3Y2Y1) instead of (Y4Y3Y2Y1)
X4X3X2X1
Y4Y3Y2Y1

26. BCD Adder
When the sum of two digits is less than or equal to 9 then the ordinary 4-bit adder can be used
But if the sum of two digits is greater than 9 then a correction must be added “I.e adding 0110”
We need to design a circuit that is capable of doing the correct addition

27. Examples : 1. CASE I : Sum <= 9 & carry = 0.
Add BCD digits 3 & 4
Answer is valid BCD number = (7)BCD & so addition of 0110 is not added.

28. 2. CASE II : Sum > 9 & carry = 0.
Add BCD digits 6 & 5
Invalid BCD (since sum > 9) so 0110 is to be added
( )BCD
Valid BCD result = (11) BCD

29. 3. CASE III : Sum < = 9 & carry = 1.
Add BCD digits 9 & 9
Invalid BCD ( since Carry = 1 ) so 0110 is to be added
( )BCD
Valid BCD result = (18) BCD

30. Design of BCD Adder Design of BCD adder :
To execute first step i. e. binary addition of two 4 bit numbers we will use IC 7483 ( with Cin = 0 ), which is 4 bit binary adder.
We need to design a digital circuit which will sense sum & carry of IC 7483 & if sum exceeds 9 or carry = 1, this digital circuit will produce high output otherwise its output will be zero.

31. Design of BCD Adder
The cases where the sum of two 4-bit numbers is greater than 9 are in the following table: S4 S3 S2 S1 S0 1 10 11 12 13 14 15 16 17 18

32. BCD Adder Whenever S4=1 (sums greater than 15)
Whenever S3=1 and either S2 or S1 or both are 1 (sums 10 to 15)
The previous table can be expressed as:
X = S4 + S3 ( S2 + S1)
So, whenever X = 1 we should add a correction of 0110 to the sum.

33. Inputs:[A]=0101, [B]= 0011, Co=0
0011
0101
1000 1
0000

34. Inputs:[A]=0111, [B]= 0110, Co=0
0110
0111 1 1 1
1101 1
0110

35. Cascading BCD Adders
The previous circuit is used for adding two decimal digits only. That is, “ = 13”.
For adding numbers with several digits, a separate BCD adder for each digit position must be used.
For example: ?
BCD Adder

36. Cascading BCD Adders

37. Example
Determine the inputs and the outputs when the above circuit is used to add 538 to 247. Assume a CARRY IN = 0
Solution:
Represent the decimal numbers in BCD = =
Put these numbers in registers [A] and [B]
[A] =
[B] =

38. Example
0101 1
1000
0111

39. BCD Subtractor Rules for BCD subtraction :
1. Find 9’s complement of the subtrahend.
a) To find 9’s complement first find 1’s complement of subtrahend.
b) Add (10)10 i.e. (1010)2 to it.
2. Add 9’s complement of the subtrahend to the minuend using BCD rules of addition.
3. After BCD addition if MSD is 0, result is negative expressed in 9’s
complement form to get it in natural form find 9’s complement of the LSD of the result.
4. But after BCD addition if MSD is 1 it indicates that result is positive expressed in natural form & add ( 1 )10 i. e. ( 0001 )2 to it.

40. CASE I : carry = 1, answer is positive
Subtract BCD digit 2 from 8.
1. 9’s complement of (2)10 i.e. (0010)2
a) 1’s complement of (2)
b) add (1010)
(discard carry).
(8)10
’s comp. of (2)10
Invalid BCD so (0110)2 is added
Since MSD after BCD addition is 1, answer is positive expressed in natural form & to get final answer carry is added at the end
i. e. (6)10

41. CASE II : carry = 0, answer is negative
Subtract BCD digit 9 from 6.
1. 9’s complement of (9)10 i.e. (1001)2
a) 1’s complement of (9)
b) add (1010)
(discard carry).
(6)10
’s comp. of (9)10
valid BCD with carry = 0
Since MSD after BCD addition is 0, answer is negative expressed in 9’s compliment form & to get final answer, 9’s compliment of answer is taken .
a) 1’s complement of answer
b) add (1010)
(discard carry).
So final answer is –(3)10 i.e.- (0011)

42. Design of BCD Subtractor
1. To execute first step i. e. to find 9’s compliment of subtrahend
a) First we find 1s compliment of subtrahend.
b) Then add (10)10 i.e. (1010)2 to 1’s compliment of subtrahend.
We use inverter to get 1’s compliment of subtrahend since subtrahend is 4 bit we need 4 inverters and to add this to (1010)2, 4 bit binary adder IC 7483 is used.
2. Circuit for BCD addition of 9’s compliment of subtrahend and minuend we will use already designed BCD adder
3. Circuit to get answer in correct form.
If MSD after BCD addition is 0, answer is negative expressed in 9’s compliment form & to get answer in correct form we have to find 9’s compliment of the result.
If MSD after BCD addition is 1, answer is positive expressed in natural form & to get final answer carry is added to the earlier answer.

43. Logic Diagram

44. CIRCUIT DELAYS (1/5)
Given a logic gate with delay t. If inputs are stable at times t1, t2, …, tn, then the earliest time in which the output will be stable is: max( t1, t2, …, tn ) + t t1
Logic
Gate t2 tn :
max (t1, t2, ..., tn ) + t
To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

45. CIRCUIT DELAYS (2/5)
As a simple example, consider the full adder circuit where all inputs are available at time 0. Assume each gate has delay t. X Y S C Z 

46. CIRCUIT DELAYS (3/5) More complex example: 4-bit parallel adder. C1
Y1 X1 S1 FA C2 C5
Y2 X2 S2 C3
Y3 X3 S3 C4
Y4 X4 S4

47. CIRCUIT DELAYS (4/5) Analyse the delay for the repeated block. Xi Yi
where Xi, Yi are stable at 0t, while Ci is assumed to be stable at mt.
Full
Adder Xi Yi Ci Si
Ci+1 mt
Performing the delay calculation: Xi Yi Si
Ci+1 Ci
max(0,0)+t = t t mt
max(t,mt)+t
max(t,mt)+2t

48. CIRCUIT DELAYS (5/5) Calculating:
When i=1, m=0; S1 = 2t and C2 = 3t
When i=2, m=3; S2 = 4t and C3 = 5t
When i=3, m=5; S3 = 6t and C4 = 7t
When i=4, m=7; S4 = 8t and C5 = 9t
In general, an n-bit ripple-carry parallel adder will experience the following delay times:
Sn = ?
Cn+1 = ?
Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles.

49. FASTER CIRCUITS Three ways of improving the speed of circuits:
Use better technology (eg. ECL faster than TTL gates) BUT
Faster technology is more expensive, needs more power, lower-level of integrations
Physical limits (eg. speed of light, size of atom)
Use gate-level designs to two-level circuits! (use sum-of-products/product-of-sums) BUT
Complicated designs for large circuits
Product/sum terms need MANY inputs!
Use clever look-ahead techniques BUT
There are additional costs (hopefully reasonable).

50. LOOK-AHEAD CARRY ADDER (1/6)
Consider the FA, where intermediate signals are labelled as Pi and Gi:
Pi = Xi  Yi
Gi = Xi ∙Yi Xi Yi Si
Ci+1 Ci Pi Gi
The outputs Ci+1, Si, in terms of Pi, Gi, Ci are:
Si = Pi  Ci … (1)
Ci+1 = Gi + Pi∙Ci … (2)
Looking at equation (2):
Gi = Xi ∙Yi is a carry generate signal, and
Pi = Xi  Yi is a carry propagate signal.

51. LOOK-AHEAD CARRY ADDER (2/6)
For 4-bit ripple-carry adder, the equations for the four carry signals are:
Ci+1 = Gi + Pi∙Ci
Ci+2 = Gi+1 + Pi+1∙Ci+1
Ci+3 = Gi+2 + Pi+2∙Ci+2
Ci+4 = Gi+3 + Pi+3∙Ci+3 Ci Pi
Ci+1 Gi
Pi+1
Gi+1
Ci+2
4-level circuit for Ci+2 = Gi+1 +Pi+1.Ci+1
These formulae are deeply nested, as shown here for Ci+2:

52. LOOK-AHEAD CARRY ADDER (3/6)
Nested formulae/gates cause more propagation delay.
Reduce delay by expanding and flattening the formulae for carries. Example, for Ci+2:
Ci+2 = Gi+1 + Pi+1∙Ci+1
= Gi+1 + Pi+1∙(Gi + Pi∙Ci)
= Gi+1 + Pi+1∙Gi + Pi+1∙Pi∙Ci
New faster circuit for Ci+2: Ci Pi
Pi+1 Gi
Gi+1
Ci+2

53. LOOK-AHEAD CARRY ADDER (4/6)
Other carry signals can be similarly flattened:
Ci+3 = Gi+2 + Pi+2∙Ci+2
= Gi+2 + Pi+2∙(Gi+1 + Pi+1∙Gi + Pi+1∙Pi∙Ci)
= Gi+2 + Pi+2∙Gi+1 + Pi+2∙Pi+1∙Gi + Pi+2∙Pi+1∙Pi∙Ci
Ci+4= Gi+3 + Pi+3∙Ci+3
= Gi+3 + Pi+3∙(Gi+2 + Pi+2∙Gi+1 + Pi+2∙Pi+1∙Gi + Pi+2∙Pi+1∙Pi∙Ci)
= Gi+3 + Pi+3∙Gi+2 + Pi+3∙Pi+2∙Gi+1 + Pi+3∙Pi+2∙Pi+1∙Gi +
Pi+3∙Pi+2∙Pi+1∙Pi∙Ci
Note that formulae gets longer with higher carries.
Also, all carries are two-level sum-of-products expressions, in terms of the generate signals Gs, the propagate signals Ps, and the first carry-in Ci.

54. LOOK-AHEAD CARRY ADDER (5/6)
We employ look-ahead formula in this lookahead-carry adder circuit:

55. LOOK-AHEAD CARRY ADDER (6/6)
The IC chip allows faster lookahead adder to be built.
Assuming gate delay is t, maximum propagation delay for circuit is hence 4t
t to get generate and propagate signals
2t to get the carries
t for the sum signals

56. Code Converter Binary to Gray Code Gray to Binary Code
BCD to Excess – 3 Code
Excess-3 to BCD Code

57. Binary To Gray Conversion
Gray To Binary Conversion

58. Binary To Gray Code Conversion:
Truth Table:
Binary To Gray Code Conversion
INPUT (BINARY CODE)
OUTPUT (GRAY CODE) B3 B2 B1 B0 G3 G2 G1 G0 1

59. K-Map For Reduced Boolean Expressions Of Each Output:

60. 3) Circuit Diagram for Binary to Gray Code Conversion

61. Gray To Binary Code Conversion:
Truth Table: Gray To Binary Code Conversion
INPUT (GRAY CODE)
OUTPUT (BINARY CODE) G3 G2 G1 G0 B3 B2 B1 B0 1

62. K-Map For Reduced Boolean Expressions Of Each Output:
Fig. 7 Logical Circuit Diagram for Gray to Binary Code Conversion

63. Circuit Diagram: