1. 65 nm technology for HEP: status and perspectives Pierpaolo Valerio, CERN on behalf of the RD53 collaboration

2. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 2

3. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 3

4. Facing new challenges ATLAS and CMS phase 2 pixel upgrades, as well as CLIC, require advanced vertex detectors: Very high particle rates: 500MHz/cm 2 Smaller pixels: ~1/6 (~50x50 µ m 2, ~25x25 µ m 2 ) Increased readout rates: 100kHz -> ~1MHz Low mass -> Low power Unprecedented hostile radiation: 1 Grad, 10 16 Neu/cm 2  10x increase! For the LHC phase 2: complex, high rate and radiation hard pixel chips (see talks by J. Grosse- Knetter and M. Musich) For CLIC: very high density, low power designs (see talk by S. Redford) pierpaolo.valerio@cern.ch19/10/2014 4

5. The need for a new technology A more downscaled technology can help achieving the needs for future developments in HEP Higher density Lower power consumption Allows for faster and more complex designs Better suited for “mostly digital” designs Potentially better radiation hardness Drawbacks include: Higher costs More complex development pierpaolo.valerio@cern.ch19/10/2014 5

6. Why 65 nm? High density and low power Mature technology: ▫Available since ~2007 Long term availability (Relatively) affordable (MPW availability, but ~1 M$ NRE for final chips!) Significantly increased density, speed and complexity pierpaolo.valerio@cern.ch19/10/2014 6

7. “Moore’s law” for pixel detectors CMOS process [µm] Tr a n si st o r d e n si ty p e r pi x el a r e a [t r a n si st o rs / µ m 2 ] Medipix1 (1998) Medipix2 (2002) Medipix3RX (2012) Timepix3 (2013) CLICpix (2013) – 65 nm FEI3 (2003) FEI4 (2011) PSI46 (2005) Rad-Hard designs pierpaolo.valerio@cern.ch19/10/2014 7

8. Risks and issues to address Deep submicron technologies are not designed primarily for analog designs. ▫Lower power supply voltage  lower dynamic range ▫Process spread and device mismatch is worse for smaller devices More complex design rules and guidelines for design for manufacturing Radiation performances need to be studied pierpaolo.valerio@cern.ch19/10/2014 8

9. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 9

10. RD53: ATLAS-CMS-CLIC collaboration RD53 is a collaboration between ATLAS, CMS and CLIC to set the ground to develop next generation of pixel readout chips RD53 was organized to tackle the extreme and diverse challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments (LHC – phase II upgrade of ATLAS and CMS, CLIC) 19 Institutes ▫Bari, Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab, LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico, Padova, Perugia, Pisa, Prague IP/FNSPE-CTU, PSI, RAL, Torino, UC Santa Cruz. ~100 collaborators pierpaolo.valerio@cern.ch19/10/2014 10

11. RD53 working groups RD53 is split in six different working groups: Radiation Tolerance Simulation Analog Top level IP Blocks I/O interfaces pierpaolo.valerio@cern.ch19/10/2014 11

12. RD53 timescale 2014: ▫Detailed understanding of radiation effects in 65nm ▫Simulation framework with realistic hit generation and auto- verification. ▫Common MPW submission 1: First versions of IP blocks and analog FEs 2015: ▫Common MPW submission 2: Near final versions of IP blocks and FEs. ▫Common MPW submission 3: Final IPs and FEs, Initial pixel array(s) 2016: ▫Common engineering run: Full sized pixel array chip. 2017: ▫Separate or common ATLAS – CMS final pixel chip submissions. pierpaolo.valerio@cern.ch19/10/2014 12

13. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 13

14. TID radiation effects: NMOS devices After 1000 Mrad : transconductance loss is between 20% and 40% The loss is still higher for narrower devices pierpaolo.valerio@cern.ch19/10/2014 14 -25C25C100C

15. TID radiation effects: PMOS devices For high level of dose (1000 Mrad), transconductance decrease reaches 100% for 120 nm and 240nm devices pierpaolo.valerio@cern.ch19/10/2014 15 -25C25C100C

16. Low temperature measurements T room: ▫The transconductance decay reaches 80% and more for the narrowed devices (~100% for 120n & 240n) -15°C: ▫the decrease was less pronounced for low T, 35% and less excepted the 120n (55%) T room -15°C M. Barbero et al, CCPM pierpaolo.valerio@cern.ch19/10/2014 16

17. Effect on digital structures Ring oscillator 2014 test at –25C For same sized inverter: ▫-10% @200Mrad ▫-35% @1Grad 65nm cross-section is proportional to the 4x reduction in area Bonacini, CERN pierpaolo.valerio@cern.ch19/10/2014 17

18. Possible front-end architectures The classical continuous- time analog processing channel is a well- established solution for pixel sensors in high- energy physics In an advanced CMOS process, a synchronous architecture may be a good alternative, with self- calibration and discrete- time signal processing features (correlated double sampling, autozeroing) clocked by the bunch- crossing cadence Synchronous comparator Asynchronous Architecture INFN-TO INFN-PV/BG pierpaolo.valerio@cern.ch19/10/2014 18

19. Analog/Digital integration A correct layout is crucial to avoid digital interferences in the low-noise analog front-end Quiet configuration logic VDDA VDD D GND D GNDA Just as for digital columns, digital cores can be subdivided into regions for hit and latency memory sharing. Physical layout must be optimized for bandwidth, clock distribution and other constraints Abder Mekkaoui, RD53 pierpaolo.valerio@cern.ch19/10/2014 19

20. Required Bandwidth The bandwidth and hit-rate are major challenges The estimation is 1 MHz trigger rate, which leads to a BW of 4 Gbps/chip  too high New readout architectures are needed: On-chip data compression On-chip clustering Reduced information for some layers Readout electronics with bandwidths comparable to high-speed memory chips! M. Garcia-Sciveres, Berkeley National Lab pierpaolo.valerio@cern.ch19/10/2014 20

21. Standard IP blocks A Working Group is dedicated to the development of standard IP blocks Effort is going on in defining guidelines on how to build, test, document and distribute IP blocks A common IP blocks repository will greatly decrease development time for future projects and will increase their success, by using blocks which were already tested and validated pierpaolo.valerio@cern.ch19/10/2014 21

22. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 22

23. CLICpix CLICpix is a hybrid pixel detector to be used as the CLIC vertex detector Main features: ▫small pixel pitch (25 μm), ▫Simultaneous TOA and TOT measurements ▫Power pulsing ▫Data compression A demonstrator of the CLICpix architecture with an array of 64x64 pixels has been submitted and tested 1.85 mm 3 mm pierpaolo.valerio@cern.ch19/10/2014 23

24. The analog front-end shapes photocurrent pulses and compares them to a fixed (configurable) threshold Digital circuits simultaneously measure Time-over-Threshold and Time-of-Arrival of events and allow zero-compressed readout Input CSA 4-bit Th.Adj DAC Feedback network Polarity TOA ASM TOT ASM Clk divider 4-bit TOT counter 4-bit TOA counter HF Bottom pixel Top pixel Configuration data: Th.Adj, TpulseEnable, CountingMode, Mask Threshold V test_pulse Clock Pixel architecture pierpaolo.valerio@cern.ch19/10/2014 24

25. Pixel logic summary Technology65 nm (High-Vt Standard Cells), Asynchronous State Machines Pixel size25x25 µm 25x14 µm (Analog) 25x11 µm (Digital) Acquired DataTOT and TOA Counter Depth (LFSR)4 bits TOT + 4 bits TOA (or counting, for calibration) Target Clock Speed100 MHz (acquisition) 320 MHz (readout) Data typeFull Frame Zero compression (pixel, super- pixel and column skipping) Acquisition TypeNon-continuous Power SavingClock gating (digital part), Power gating (analog part) pierpaolo.valerio@cern.ch19/10/2014 25

26. A simple block diagram Data IN Data OUT Analog part of adjacent pixels share biasing lines. Digital part is shared between each two adjacent pixels 64x64 pixel matrix Chip periphery pierpaolo.valerio@cern.ch19/10/2014 26 200 μ m 50 μ m

27. Measurement summary SimulationsMeasurement TOA Accuracy< 10 ns Gain 44 mV/ke - 40 mV/ke - Dynamic Range up to 40 ke - (configurable) Non-Linearity (TOT) < 8% at 40 ke - < 4% at 40 ke - Equivalent Noise (no sensor capacitance) ~60 e - ~51 e - (with 10% variation r.m.s.) DC Spread (uncalibrated) σ = 160 e - σ = 128 e - DC Spread (calibrated) σ = 24 e - σ = 22 e - Analog pixel power consumption (while ON) 6.5 μ W7 μ W 27 Measurements expressed in electrons depend on capacitance values. A nominal value of 10 fF was assumed here for the test capacitor pierpaolo.valerio@cern.ch19/10/2014

28. Radiation Testing The chip was irradiated up to 800 Mrads. Above 200Mrad, the chip gradually turned off, as damaged switches used for biasing structures are unable to let the nominal current pass (their driving current becomes too low). All I/O interfaces and digital structures did not show any significant degradation during irradiation, even after the analog front-end stopped working The chips regained some functionality after two week of annealing at room temperature (the total power consumption went back to pre-rad value). Analog performances of the measured chip were found to be considerably degraded. pierpaolo.valerio@cern.ch19/10/2014 28

29. Lessons learned Feasibility of high density pixel chips with advanced features using 65 nm technology has been proved Design flow using new software tools was established, simulation models have been validated The main challenges include analog/digital integration and design of high performances analog structures pierpaolo.valerio@cern.ch19/10/2014 29

30. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 30

31. Other 65 nm projects MPA (Macro Pixel ASIC) - CERN ▫Front-end to be used CMS tracker upgrades for HL-LHC ▫100 x 1446 μ m pixels ▫Modules with local p T discrimination LpGBT - CERN ▫Low-power/small-footprint version of GPT chip Gigabit transmitter for the BELLE-II pixel detector – University of Bonn (see talk by M. Schnell) pierpaolo.valerio@cern.ch19/10/2014 31

32. Outline The push for a more downscaled technology RD53 collaboration New developments and challenges A first prototype: CLICpix Other projects Conclusions pierpaolo.valerio@cern.ch19/10/2014 32

33. Conclusions and next steps Design work has started in 65nm (FEs, IPs) ▫The technology has been validated and it can help face the challenges of a new generation of pixel detectors ▫Functionality of this CMOS process has been proved in CLICpix and it will be studied further in a number of new chips being developed in the following months/years Radiation performance is good, but it has to be studied for extremely high doses Work must be done to build IPs and research new architectures which can take advantage of a more downscaled process pierpaolo.valerio@cern.ch19/10/2014 33

34. pierpaolo.valerio@cern.ch19/10/2014 34

35. pierpaolo.valerio@cern.ch19/10/2014 35

36. Facing new challenges Current LHC pixel detectors have clearly demonstrated the feasibility and power of pixel detectors for tracking in high rate environments Phase 2 upgrades: ~16x hit rates, ~4x better resolution, 10x trigger rates, 16x radiation tolerance, increased forward coverage, less material… Relies fully on significantly improved performance from next generation pixel chips pierpaolo.valerio@cern.ch19/10/2014 36

37. Radiation effects in 65 nm CMOS Thin (rad-hard) gate oxide for core devices, becomes thicker (and rad-softer) for I/O transistors Thick Shallow Trench Isolation Oxide (~ 300 nm); radiation- induced charge-buildup may turn on lateral parasitic transistors and affect electric field in the channel) Doping profile along STI sidewall is critical; doping increases with CMOS scaling, decreases in I/O devices N+N+ N+N+ G S D P- well STI P-substrate Increasing sidewall doping makes a device less sensitive to radiation (more difficult to form parasitic leakage paths) Spacer dielectrics may be radiation-sensitive pierpaolo.valerio@cern.ch19/10/2014 37

38. TOT measurements  TOT gain variation is 4.2% r.m.s.  Tested for nominal feedback current  Corners have lower TOT gain  TOT integral non-linearity for different feedback currents was tested  TOT dynamic range matches simulations pierpaolo.valerio@cern.ch19/10/2014 38

39. Threhsold equalization Routines for equalizing the threshold using the pixel calibration DACs were implemented, finding the noise floor for all pixels Calibrated spread is 0.89 mV (about 22 e - assuming a 10 fF test capacitance) across the whole matrix pierpaolo.valerio@cern.ch19/10/2014 39