1. © 2000 Morgan Kaufman Overheads for Computers as Components CPUs zCPU performance: How fast it can execute instructions  increasing throughput by pipelining zCPU power consumption.

2. © 2000 Morgan Kaufman Overheads for Computers as Components Elements of CPU performance zCycle time: How fast CPU executes an instruction zCPU pipeline: Modern CPUs are pipelined machines zMemory system: Can affect overall performance.

3. © 2000 Morgan Kaufman Overheads for Computers as Components Pipelining zSeveral instructions are executed simultaneously at different stages of completion. zVarious conditions can cause pipeline bubbles that reduce utilization: ybranches; ymemory system delays;

4. © 2000 Morgan Kaufman Overheads for Computers as Components Pipeline structures zBoth ARM and SHARC have 3-stage pipes: yfetch instruction from memory; ydecode opcode and operands; yexecute. z Without pipeline we need at least 3 cycles to complete an instruction zWith pipeline 1 cycle (on average)

5. © 2000 Morgan Kaufman Overheads for Computers as Components ARM pipeline execution add r0,r1,#5 sub r2,r3,r6 cmp r2,#3 fetch time decode fetch execute add decode fetch execute sub decode execute cmp 123

6. © 2000 Morgan Kaufman Overheads for Computers as Components Performance measures zLatency: time it takes for an instruction to get through the pipeline: 3 clock cycles zThroughput: number of instructions executed per time period: 1/cycle zPipelining increases throughput without reducing latency.

7. © 2000 Morgan Kaufman Overheads for Computers as Components Pipeline stalls: Instructions too complex to complete in one cycle zIf every step cannot be completed in the same amount of time, pipeline stalls. zBubbles introduced by stall increase latency, reduce throughput.

8. © 2000 Morgan Kaufman Overheads for Computers as Components ARM multi-cycle LDMIA (load multiple) instruction fetchdecode ex ld r2 ldmia r0,{r2,r3} sub r2,r3,r6 cmp r2,#3 ex ld r3 fetch time decode ex sub fetchdecode ex cmp Decode stage occupied since ldmia must continue to remember decoded instruction sub fetched at normal time but not decoded until LDMIA is finishing Instruction delayed

9. © 2000 Morgan Kaufman Overheads for Computers as Components Control stalls: due to branches zBranches often introduce stalls (branch penalty). yStall time may depend on whether branch is taken. zMay have to squash instructions that already started executing. zDon’t know what to fetch until condition is evaluated.

10. © 2000 Morgan Kaufman Overheads for Computers as Components ARM pipelined branch time fetchdecode ex bne bne foo sub r2,r3,r6 fetchdecode foo add r0,r1,r2 ex bne fetchdecode ex add ex bne Decision not made until the third clock cycle Two cycles of work thrown away if bne takes place

11. © 2000 Morgan Kaufman Overheads for Computers as Components CPU power consumption zMost modern CPUs are designed with power consumption in mind to some degree. zPower vs. energy: yheat depends on power consumption; ybattery life depends on energy consumption.

12. © 2000 Morgan Kaufman Overheads for Computers as Components CMOS power consumption zVoltage drops: power consumption proportional to V 2. z P = ½ f C V 2 (CMOS Inverter circuit) zToggling: more activity means more power  Reducing speed reduces power zLeakage: basic circuit characteristics; can be eliminated by disconnecting power.

13. © 2000 Morgan Kaufman Overheads for Computers as Components CPU power-saving strategies zReduce power supply voltage. zRun at lower clock frequency. zDisable function units with control signals when not in use. zDisconnect parts from power supply when not in use.

14. © 2000 Morgan Kaufman Overheads for Computers as Components Power management styles zStatic power management: does not depend on CPU activity. yExample: user-activated power-down mode. Entered by an instruction. zDynamic power management: based on CPU activity. yExample: disabling off function units, e.g., certain CPU sections when instructions do not need them

15. © 2000 Morgan Kaufman Overheads for Computers as Components Power-down costs zGoing into a power-down mode costs: ytime; yenergy. zMust determine if going into mode is worthwhile  Initialization may take time and energy zCan model CPU power states with power state machine.

16. © 2000 Morgan Kaufman Overheads for Computers as Components Application: StrongARM SA-1100 power saving zProcessor takes two supplies: yVDD is main 3.3V supply  powers the CPU core yVDDX is 1.5V  other logic, e.g., power manager zThree power modes: yRun: normal operation. yIdle: stops CPU clock, with logic still powered, e.g., clock, o/s timers, general purpose IO  Sleep: shuts off most of chip activity; 3 steps, each about 30  s; wakeup takes > 10 ms.

17. © 2000 Morgan Kaufman Overheads for Computers as Components SA-1100 Power States run idle sleep P run = 400 mW P idle = 50 mW P sleep = 0.16 mW 10  s 90  s 160 ms 90  s Long time!

18. © 2000 Morgan Kaufman Overheads for Computers as Components Assignment zQ3-1, Q3-5 (Assume arguments, return values, and return addresses are stored on the stack), Q3- 24, Q3-31, Q3-33 Graduate students: Do a survey on a processor for the following features: Memory management, power saving modes.