1. CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC Gianluca Traversi 1,2 (gianluca.traversi@unibg.it), Massimo Manghisoni 1,2 (massimo.manghisoni@unibg.it), Lodovico Ratti 2,3 (lodovico.ratti@unipv.it), Valerio Re 1,2 (valerio.re@unibg.it), Valeria Speziali 2,3 (valeria.speziali@unipv.it) Introduction In the last few years several groups proposed the application of CMOS Monolithic Active Pixel Sensors (MAPS), initially developed for imaging applications, as tracking devices for ionizing particles in high energy physics experiments. This work is intended to discuss the features of a novel kind of monolithic active pixel sensors (MAPS) in deep submicron CMOS technology (130 nm minimum feature size) for use in charged particle trackers and vertex detectors. As compared to conventional MAPS with 3-transistor readout scheme, the design approach proposed here, where a deep N-well (DNW) is used as the collecting electrode, lends itself to pixel-level sparsified processing and is expected to provide the ability to manage the large data flow of information anticipated for future, high luminosity colliders. Lately, the applicability of the DNW-MAPS concept to the design of the vertex detector for future high luminosity colliders, like the International Linear Collider (ILC), has been investigated. This paper will discuss the design and performance of a recently submitted DNW monolithic sensor, the SDR0 (Sparsified Digital Readout) chip, including different test structures, where both analog (charge amplification and threshold discrimination) and digital (sparsification, time stamping) functions have been integrated inside the elementary sensor, as large as 25m x 25m. 1 Università di Bergamo Dipartimento di Ingegneria Industriale, I-24044 Dalmine (BG), Italy 3 Università di Pavia Dipartimento di Elettronica, I-27100 Pavia, Italy 2 INFN Sezione di Pavia I-27100 Pavia, Italy Prototype Design Conclusions In this paper we presented the design of a DNW-MAPS prototype chip tailored for vertexing applications at the ILC experiments. This device features a sparsified readout architecture, and time stamping capabilities and ensures low digital power consumption and a significant reduction in the amount of data sent off chip. Overall power consumption is very close to the specifications set for the Large Detector Concept at the ILC. In order to comply with the resolution constraints of the ILC vertex detector, new design solutions for the in-pixel time stamp register are being investigated, together with possible scaling down of the design to the next generation CMOS technology. Cell Analog Front-End MAPS sensor operation in the prototype chip is tailored on the structure of the ILC beam and features two different processing phase: detection phase (corresponding to the bunch train period), readout phase (corresponding to the intertrain period). Preamplifier response to an 800 e - pulse IFIF During the detection phase the time stamp is sent to all cells. When a pixel is hit during the detection phase, the SR-FF output goes high and the time stamp gets frozen. At the end of the detection phase a token is launched and a sparse readout is performed row by row. During the readout phase, the hit cell, after the arrival of the token, sends both the coordinate and time stamp data to the output serializer at the next cell clock rising edge. Digital information relevant to each single hit cell is serialized and transmitted off the chip within a cell clock period. The number of elements may be increased without changing the pixel logic (just larger X- and Y-registers and serializer will be required). Digital section and sparsified readout architecture ILC Vertex Detector Requirements Physical simulations show that for a linear e + -e - collider operated at 500 GeV, a maximum hit occupancy of 0.03 particles/crossing/mm 2 can be considered a reasonable assumption in the innermost layer of the detector. If charge spreading in the epitaxial layer and interpixel hits are accounted for, 3 pixels can be expected to fire for every particle hitting the detector. Thus the hit rate on the innermost cylinder is about 250 hits/train/mm 2. Cell layout 25 m DNW sensor Preamplifier + Discriminator Time stamp register Sparsification logic 25 m Further pitch reduction might be achieved by: replacing the digital time stamp register with an analog one using a further scaled process, namely a 90 nm CMOS technology by STM, supposed to have substrate features similar to those of the 130 nm process If a binary readout approach is adopted, a resolution position better than 5 micron requires a square pixel with a pitch smaller than 17.5 m. If a 17.5 m pitch is assumed, then the occupancy for a single cell is close to 0.076 hits/train. Given these figures, the probability of a cell being hit at least twice is 0.3%, which means that a pipeline with a depth of one would be sufficient to record around 99.7% of the events without any ambiguity. Power consumption: 5 μW Equivalent noise charge: 30 e - rms @ C D =100 fF Threshold dispersion: 30 e - (main contributions from preamplifier input device and NMOS and PMOS pairs in the discriminator)