1. 1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design

2. CS 151 2 Overview Part 1 – Design Procedure  Steps Specification Formulation Optimization Technology Mapping  Beginning Hierarchical Design  Technology Mapping - AND, OR, and NOT to NAND or NOR  Verification Manual Simulation

3. CS 151 3 Overview (continued) Part 2 – Combinational Logic  Functions and functional blocks  Rudimentary logic functions  Decoding using Decoders Implementing Combinational Functions with Decoders  Encoding using Encoders  Selecting using Multiplexers Implementing Combinational Functions with Multiplexers

4. CS 151 4 Design Procedure 1. Specification  Write a specification for the circuit if one is not already available Determine and name inputs Determine and name outputs 2. Formulation (Truth table)  Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification 3. Optimization  Simplify the resulting Boolean functions for each output 4. Draw Logic Diagram 5. Technology Mapping  Transform the logic diagram to a new diagram using the available implementation technology. 6. Verification  Verify the correctness of the design Sections 3-4 and 3-6

5. CS 151 5 Example-1 Design a combinational circuit with 3 inputs and 1 output. The output must be logic 1 when the binary value of the inputs is less than 011(3) and logic 0 otherwise. Use only NAND Gates.

6. CS 151 6 Example-1 (Cont) 3. Boolean Function for each output F = ? 4. Logic Diagram and Technology Mapping 1. Specification: 3 inputs : X, Y and Z 1 output: F 2. (Formulation) Truth Table 3 inputs  2 3 rows

7. CS 151 7 Example-2 Design a BCD to Excess-3 code converter  Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits  BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively  Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word

8. CS 151 8 BCD-to-Excess-3 Code Converter BCD codeExcess-3 code 00000000 11001100 11101110 01010101 Example-2 (Cont.)  In multiple output circuits, each output must be expressed separately as a function of all the input variables

9. CS 151 9 1. Specification: 4 Inputs: A, B, C and D 4 Outputs: W,X, Y and Z Don’t cares: BCD 1010 to 1111 2. Formulation (Truth Table) 4 inputs  2 4 rows BCD only needs 10 rows Design of a BCD-to-Excess-3 Code Converter Example-2 (Cont.) W=  (5,6,7,8,9) X=  (1,2,3,4,9) Y=  (0,3,4,7,8) Z=  (0,2,4,6,8)

10. CS 151 10 3. Optimization Boolean function for each output using K-maps B C D A 0132 4576 12131514 891110 1 11 1 XXX XX X 1 B C D A 0132 4576 12131514 891110 11 1 1 XXX XX X 1 B C D A 0132 4576 12131514 891110 11 1 XXX XX X 1 1 w y x Example-2 (Cont.) W=  (5,6,7,8,9) X=  (1,2,3,4,9) Y=  (0,3,4,7,8) Z=  (0,2,4,6,8) B C D A 0132 4576 12131514 891110 1 11 1 XXX XX X 1 z W= A + BC + BD = A + B(C+D) X = B’C + B’D + BC’D’ = B`(C+D) + BC`D` Y = CD + C’D’ Z = D’

11. CS 151 11 Example-2 (Cont.) 4. Draw the logic diagram W= A + B(C+D) X = B`(C+D) + BC`D` Y = CD + C’D’ Z = D’

12. CS 151 12 Design a BCD-to-Seven-Segment Decoder A BCD-to-seven-segment-decoder is a combinational circuit that accepts a decimal digit in BCD and generates the appropriate output for the selection of segments that display the decimal digit. Each digit is formed from 7 segments, each consisting of 1 LED that can be illuminated by digital signals. Example 3

13. CS 151 13 BCD code 11111111111111 BCD-to-7-Segment Decoder 00010001 Example 3 (Cont.) 1.Specification:   4 Inputs (BCD bits): A, B, C and D  7 Outputs (display segments): a, b, c, d, e, f and g  Don’t cares: BCD 1010 to 1111 g f e d c b a A B C D

14. CS 151 14 2. Formulation (Truth table) : 2. Formulation (Truth table) To display the input BCD digit :  Which segment(s) should illuminate (be turned on)?  Which segment(s) should not illuminate (be turned off)? a b c d e f g Example 3 (Cont.)

15. CS 151 15 3. Optimization: 3. Optimization: Boolean Function for each output  a=? b=? c=? d=?  e=? f=? g=? 4. Draw the logic diagram Example 3 (Cont.)