1. Introduction to ASIC flow and Verilog HDL

2. What is Verilog ?
IEEE industry standard Hardware Descriptive Language (HDL) – used to describe a digital system
Used in both hardware simulation and synthesis
HDL : A text programing language used for model a piece of hardware

3. More Terminology:
Register Transfer Level : A type of behavioral modeling, for the purpose of synthesis.
Synthesis : Translating HDL to a circuit and then optimizing the represented circuit.
RTL Synthesis : Translating the RTL model of hardware into an optimized technology specific gate level implementation.

4. What is Synthesis?

5. Synthesis Implementation (Basic)

6. Basic VLSI Design Flow:

7. Synthesis vs Simulation

8. Synthesis Flow

9. Basics of Combinational Digital Design
Using a NAND gate, how many ways can you come up with an Inverter?

10. Implementing an Inverter using 2:1 MUX
Equation of the Mux :
Output = S * A + S (bar) * B
If we replace A with zero and B with 1 we get the functionality of an Inverter
Output = S * 0 + S (bar) * 1
Output = S (bar)
You can verify using truth tables, the following circuit describes an inverter using 2:1 MUX

11. And Gate using 2:1 MUX Equation of the Mux :
Output = S * A + S (bar) * B
Tie Input B to zero we get
Output = S*A (AND gate)

12. 2:1 MUX using only NAND Gates

13. Verilog : The module

14. Behavioral Description (Continuous /Dataflow Assignment)
Continuous assignment use the assign keyword.
A simple natural way to express the circuit.
Specify the logic expression instead of describing the gate level.
HDL more useful if used as a higher level of abstraction.
The RHS is continuously evaluated as a function of arbitrarily changing
inputs
The target / output is a net driven by combinational logic

15. Implementation of a Dataflow Assignment

16. Behavioral Description (Procedural Assignment)
An alternative, often higher level of abstraction in behavioral class
Two structured procedural statements : always and initial.
Rather than specifying a circuit by Boolean expression, we use if – else (case, while, for statements)
Supports richer control structures and provides greater flexibility.

17. Mux Implementation of Procedural statement with always

18. Gate Level : Structural Description
Provides gate level details of the design.
Net represents connections between hardware elements. Nets are declared with the keyword wire
This coding style is error prone, it’s used only when we are sure about the exact circuit implementation
Verilog supports basic logic gates as primitives
: and, or, nor, NAND, XOR, XNOR, NOT, buf

19. Structural Implementation of MUX

20. Verilog Registers
In digital design registers represents memory elements.
Digital registers need a clock to operate and update their state at a particular edge.
Registers in Verilog are different from digital design, please don’t confuse
In Verilog (reg) simple means a variable that can hold value, which can be changed anytime by assigning a new one

21. Combining Procedural and Continuous

22. The case statement:
Case and if can be used interchangeably to implement conditional execution within always blocks.
Case statements can be more easily read

23. N - bit signals in verilog
2:1 MUX with 8 – bit operands.

24. Multi bit arithmetic the easy way:

25. Port Connection Implementation

26. Connecting module instantiation Ports
module Full_Adder(Cin, x, y, Cout, s);
input Cin;
input x, y;
output Cout;
output s;
wire c1, c2, s1;
Half_Add HA1(x, y, c1, s1);
Half_Add HA2(s1, Cin, c2, s);
assign Cout = c1 | c2;
endmodule

27. Basic Verilog Construct

28. Verilog Combinational Logic

29. Alternative coding style for CL

30. Combined Verilog code for Flip Flop

31. Incorrect specification in Verilog:
Use always block sensitivity list to wait for clock to change

32. Sequential vs Combinational in always block

33. Synchronous vs Asynchronous clear

34. Implementing Asynchronous/Synchronous Reset

35. Verilog Implementation for Asynch/Synch Reset

36. Synchronous vs Asynchronous -III

37. Synchronous vs Asynchronous Reset

38. Getting the best of both worlds:
Synchronize the asynchronous external reset signal.
Use this synchronous signal as input to all asynchronous flip flops.
Asynch reset FF takes less logic to implement, consumes less power.

39. The Asynchronous Metastable Problem

40. Blocking vs Non-Blocking

41. Swap function using blocking/non blocking

42. Assignment style for Sequential design

43. Use Non-Blocking for Sequential Logic

44. Use Blocking for Combinational Logic

45. Structural Representation (Revisited)

46. Structural Representation of a 4-bit Adder

49. Modeling Finite State Machines

50. Moore Machine example

51. Code for Traffic light controller

52. Traffic light controller code(contd.)

53. Further thoughts:

54. Non-latched Traffic light controller code:

55. Non-latched code (continued):

56. Moore Machine : Example 2

57. Code for parity detector:

58. Parity Detector code (continued):

59. Reasoning it’s a Moore

60. Mealy Machine : Example

61. Sequence Detector : Code

62. Sequence Detector code :(continued)

64. Example with Multiple Modules

65. The Compliment module

66. The Adder Module

67. The parity checker module

68. Top Level Module: Interconnecting the lower level modules