1. Task 2.2 Update
5th October 2011
Agrate, Milano

2. Contents
Deliverables
Completed Deliverables
Final Deliverable

3. Contents
Deliverables
Completed Deliverables
Final Deliverable

4. T2.2 Deliverables Deliverable Contributors Title D2.2.1 D.2.2.2
UNGL
Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools
D.2.2.2
UNGL, UNET,
ST-I, SNPS
Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies and and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools
D.2.2.3
UNET UNGL,
NMX, SNPS
Device simulation analysis of dominant variability sources in state-of-the-art Non-Volatile-Memory technologies

5. T2.2 Deliverables Deliverable Contributors Title D2.2.4 D.2.2.5
UNGL, IMEP,
UNET, POLI
Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation Efficient compact model extraction procedures for modeling process variations and device fluctuations
D.2.2.5
UNET, UNGL
Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations TCAD based assessment of PV effects of potential 22nm device architectures
D.2.2.6
NMX,UNGL,
STF2
Sensitivity analysis of NVM device performance as a function of individual trap position Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD Outlook to 16nm device architecture robustness using MASTAR

6. Contents
Deliverables
Completed Deliverables
Final Deliverable

7. Previously Reported D2.2.1 D.2.2.2 D.2.2.3
UNGL
Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools
D.2.2.2
UNGL, UNET,
ST-I, SNPS
Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies and and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools
D.2.2.3
UNET UNGL,
NMX, SNPS
Device simulation analysis of dominant variability sources in state-of-the-art Non-Volatile-Memory technologies

8. T2.2 Deliverables What was accomplished?
UNGL, IMEP,
UNET, POLI
Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation Efficient compact model extraction procedures for modeling process variations and device fluctuations
What was accomplished?
Statistical Variability in 32nm Bulk CMOS Technology, and in Nanowires.
Statistical Variability in DPD, SiC, GaN/AlGaN Technologies
Compact Modelling Strategies for Statistical Variability

9. D2.2.4: Statistical Variability in 32nm Bulk CMOS Technology
UNGL Contribution

10. D2.2.4: Statistical Variability in 32nm Bulk CMOS Technology
IUNET Contribution

11. D2.2.4: Statistical Variability in 32nm Bulk CMOS Technology
RVT-NMOS
RVT-PMOS
RVT-NMOS
SNPS Contribution
RVT-PMOS

12. D2.2.4: Statistical Variability in Nanowire technology
IMEP Contribution

13. D2.2.4: Statistical Variability in DPD, SiC, GaN/AlGaN Technologies
PCM STUDIO
EHD5 SEMICELL
SENTAURUS WORKBENCH
DO E
PCM
ST-I Contribution

14. D2.2.4: Statistical Variability in DPD, SiC, GaN/AlGaN Technologies
POLI Contribution

15. D2.2.4: Compact Modelling Strategies for Statistical Variability
UNGL Contribution
RVT-NMOS
RVT-PMOS

16. D2.2.4: Drain Current Variability in 45nm Bulk N-MOSFET
IMEP Contribution

17. T2.2 Deliverables What was accomplished?
UNET, UNGL
Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations TCAD based assessment of PV effects of potential 22nm device architectures
What was accomplished?
UNGL: Creation and Study of Variability in 22nm FinFET
IUNET Contribution

18. D2.2.5: UNGL: Variability in 22nm FinFET
UNGL Contribution

19. but has been completed and submitted.
D2.2.5: IUNET Contribution
Deliverable delayed
but has been completed and submitted.

20. Contents Deliverables & Timeline Completed Deliverables
Final Deliverable

21. Plans and Initial Progress
Final T2.2 Deliverable
Ref
Deliverable/ Contributors
Due date
D2.2.6
Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET,POLI,SNPS,UNGL)
Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD (SNPS,UNGL)
Outlook to 16nm device architecture robustness using MASTAR (STF2)
M36
Plans and Initial Progress

22. NMX contribution (in collab. with IUNET-MI) Task 2.2 D2.2.6
Andrea Ghetti, Augusto Benvenuti
Version 1.0

23. Investigation of RDF and RTN depedence on Substrate Doping
Investigated different doping profile varying along the length, width and depth of the device
Doping engineering in the vertical direction most effective in reducing RDF
RTN reduces more putting dopant atoms as far as possible from the interface

24. T2.2 publication list Journals
Gareth Roy, Andrea Ghetti, Augusto Benvenuti, Axel Erlebach, Asen Asenov, “Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating Gate Non-Volatile Memory”, IEEE-TED, in press
Workshops
Conferences Proceedings
A. Ghetti, S.M. Amoroso, A. Mauri, C. Monzio Compagnoni , "Doping Engineering for Random Telegraph Noise Suppression in Deca-nanometer Flash Memories“, International Memory Workshop 2011, p. 91, Monterey, CA; 5/22-25/2011

25. SNPS Contribution T2.2 D2.2.6

26. Implementations Implementation Available since Release Application
Geometrical noise analysis in 2D and 3D
Applied to 32 and 45nm bulk devices (ST Crolles, see D2.2.2 and D2.2.4), 32nm NVM (Micron, see D2.2.3), and to FinFET devices (NXP); implementation is explained in D5.3.2
Random dopant fluctuation
Implemented before project start
Applied to 32 and 45nm bulk devices (ST Crolles, see D2.2.2 and D2.2.4), 32nm NVM (Micron, see D2.2.3), and to FinFET devices (NXP)
Single traps
Ongoing work for NVM (Micron, planned for D2.2.6)
Randomization of traps
Single dopands
Deterministic fluctuations
Planned to be applied in the last year of the project
Hybrid method F
Planned to be applied to NVM (Micron), FinFET (NXP), and 32nm bulk (ST Crolles) in the last quarter of 2011
Work function variability G
Planned to be applied to FinFET (NXP) and 32nm bulk (ST Crolles) in the last quarter of 2011

27. Plan for Deliverable D2.2.6 SNPS agreed to join D2.2.6.
 We plan to apply some of the new methods implemented in Sdevice to the NVM structure.
 In detail we are thinking about the following:
Investigation of influence of single traps and single dopands on IV characteristics and gate leakage (direct statistical method).
Applying IFM hybrid method to RDF.

28. IUNET contribution for D2.2.6
Version 1.0
Alessandro Spinelli – UMET-MI in collab. with NMX
Susanna Reggiani – UNET-BO
Paolo Pavan, Luca Larcher – UNET-MORE

29. Study of RDF and RTN dependence on device geometry
Different curvature radii of the active area of template MOSFETs were considered
RDF VT distribution slightly widens for larger radii
RTN VT slope improves as curvature radius is increased

30. MODERN Progress report: IUNET-Bologna
Industrial Partner: MICRON
D – Proposed activity:
Sensitivity analysis of Non Volatile Memory device performance as a function of random dopant fluctuations (RDF). Comparison of the RDF results carried out by using Sentaurus Device and (i) the Impedance Field Method (IFM), based on the Green’s function noise calculations, or (ii) a set of randomized doping configurations generated by using the “cloud-in-cell” method.
Status: on schedule
Next steps:
Investigation of the Vth of a 32-nm Flash cell (template device)
Determination of the role played by the doping definition (see right figure).
Determination of the role played by short-channel effects (tox, LG, xj,Na).
Study of the role played by mobility by means of the IFM method.

31. IUNET – MORE Contribution: Gate current simulations
IG-VG simulation through a multi-phonon trap-assisted tunneling model
Investigation of IG temperature dependencies: carrier-limited (depletion/ /weak inversion) and transport-limited (strong inversion) regimes
Identification of the atomic configuration of the defects assisting the electron (hole) conduction in nMOS (pMOS) devices
nMOS - 1nm IL/3nm HfO2 gate stack
pMOS - 1nm IL/5nm HfO2 gate stack

32. Luca Selmi - IUNET-Udine - MODERN Progress report Nov. 2010
Progress IUNET-Udine
Task 2.2.6(b) – reference NMX: Quantization
Extremely efficient Schroedinger poisson solver for rounded corner FinFET/wire structures
More than 100x speed improvement
Example of Schr.-Poi. solution for hexagonal wire
[Paussa et al., SISPAD 2010, pp.234, accepted TED]
Luca Selmi - IUNET-Udine - MODERN Progress report Nov. 2010

33. Publications with MODERN ack.
Luca Selmi - IUNET-Udine - MODERN Progress report Nov. 2010

34. UNGL: D2.2.6 Contributions

35. UNGL D2.2.6 Plans
Sensitivity analysis of Non-Volatile Memory performance as a function of individual trap position.
Couple sensitivity of trap position to other variability sources.
Outline of GSS approach to Toolbox methodologies.

36. UNGL D2.2.6 Progress
Work in progress to look at effects of single charge trapping and sensitivity of other sources of variability to charge trapping.
NMOS
PMOS
NBTI/PBTI capabilities developed
and used in D2.4.3
Initial studies of charge trapping carried out in D2.2.3

37. UNGL D2.2.6 Toolbox
GSS GARAND
GSS Mystic
GSS RandomSpice

38. STF2 Contibution to D.2.2.6
Using analytical MASTAR model, goal is to give a first outlook on device structure impact on variability at the 16nm node. Bulk, FinFET and FDSOI will be studied interms of SNM variation and Vdd,min variation.
Test case will be a 16nm 6T-SRAM Cell
Variability will be implemented on the following device parameters : Doping, Lgate, Electrode workfunction, film thickness variation (for FD devices), and mobility
Typical 3sigma variation inputs will be based on result obtained in MODERN of 45nm/28nm technology

39. STF2 Contibution to D.2.2.6
Example of results (20nm node)