1. TDC With Hit Rate Limiter 96 Ch TDC T1 T0 DV Counter Hit Rate Limiter (7/256CK212) DVLD CLR CK212 L/S LD TDC/HRL CC[5..2] 4hits/256CK212, 4hits/1.2  s 3.3MHz CLRHITLD CLRCNT

2. TDC Data Concentration 96 Ch L1 Buffer 1xM4K 16x256 4hits/CH/1.2  s 16hits/4CH/1.2  s 1hit: 16bits Buffer Length: (256/16)x1.2  s=19.2  s Zero Supp. TDC/HRL EV Buffer 2xM4K 16x256x2 SDRAM 16x6M/spill 12MB/spill EV Window 2 x 1.2  s 128hits/16CH/EV 16 Ch Output Time: 128CK106=64RF=1.2  s 48 Ch Store Time:=3.6  s SDRAM WR Time: 256RF<4.8  s TDC/HRL L1 Buffer 1xM4K 16x256 Zero Supp. L1 Buffer 1xM4K 16x256 L1 Buffer 1xM4K 16x256 FPGA (DCC) Truncating at EV Buffer 123+5 words/48CH/EV 48 Ch Send Out Time: 128x2RF=4.8  s

3. Useful Numbers: for 96 Channel Board RF53.102MHz, 18.8ns CK212212.4MHz, 4.708ns LSB1.18ns Hit Rate Limiter Setting4hits/256CK2124hits/64RF 4hits/1.2  s, 3.3MHz Double Hit Min. Separation4xCK106, 37.7ns Event Window 2 x 1.2  s Absolute Maximum Hits/event/48ch123hits+5header/trailers128 x 2Bytes Event Maximum Size/96ch256 x 2Bytes SDRAM port data rate53MHz x 2Bytes 4.8  s/event Number of events/spill<32K Absolute Maximum data/spill/FE card8M words16MB Absolute Maximum data/spill/8 FE128MB1280Mbits Readout Chain Data Rate26.5Mbits/s Absolute Maximum Spill Readout Time48.3sec

4. Readout Timing G0 B=0 G4 B=0 G0 B=1 G4 B=1 G8 B=1 G12 B=1 G24 B=1 G8 B=0 G12 B=0 G16 B=0 G20 B=0 G16 B=1 G20 B=1 G24 B=0 G28 B=0 G28 B=1 0123456 0,1 7 6.6us 1.2us 89abc 0,1 WR RD G32 B=0 G32 B=1 G44 B=1 0,1 1.2us

5. Data Format 1CH[3..0]CC[10..2]T1T0 BD_CHGRP[4..0] CNT[7..0] EV[13..0]=1, 2,.. 16K-1 EHID[5..0] Reserved Header/Ender EV Header 0 EV Header 1 Hit Data 15141312111098765432101617 0 1 1P 1P 1P 00 000 No Data 1P CHGRP Header 000 0 TS[7..0]010 101P Ender

6. Data Block CHGRP Header CHGRP=0 EV Header 0 EV Header 1 No Data Hit Data CHGRP Header CHGRP=1 Hit Data CHGRP Header CHGRP=2 CHGRP Header CHGRP=3 Hit Data CHGRP Header CHGRP=4 CHGRP Header CHGRP=5 Ender (=No Data) CHGRP Header CHGRP=0 EV Header 0 EV Header 1 No Data Hit Data CHGRP Header CHGRP=1 CHGRP Header CHGRP=2 Ender (=No Data) EV Header 0 EV Header 1 No Data CHGRP Header CHGRP=3 Hit Data CHGRP Header CHGRP=4 CHGRP Header CHGRP=5 Ender (=No Data) Hit Data

7. TDC Description The TDC FE card has three FPGA devices: two named MIPP_TDC and one named MIPP_DCC. Each MIPP_TDC digitizes 48 channels of inputs and sends data to MIPP_DCC which interfaces with a 16MB SDRAM and the daisy-chained interface to ship data back to the controller. A TDC_FE card supports 96 input channels. Each channel in the MIPP_TDC has a hit limiter. The time is split into 1.2us (or 64RF, RF=1/53MHz) periods which are counted after the reset at the start of each spill. In each of the 1.2us, the number of hits in each channel is limited to 4 hits. A channel group contains 4 channels. Every 4 cycles of CK106 (106MHz), hit data in each channel is written to the hold-shift register. The hold-shift register then shift data of the 4 channels, one in each CK106 cycle, to the zero suppression block. Therefore, the hit separation in each channel is 4 x 1/106MHz = 37.7 ns. The zero-suppressed data from the 4-channel groups, i.e., only the valid hits are stored in the L1 pipeline buffers. A pipeline buffer is organized as 16 blocks of 16 words with 16-bit/word which uses a M4K RAM. Each hit is stored as a 16-bit word, each channel can have maximum 4 hits in 1.2us. Therefore, a 16 words block holds data of 4 channels in 1.2us. The entire L1 pipeline length is 16x1.2us = 19.3us. Up to about 18us trigger latency are supported. For each trigger, data in 2 x 1.2us time window are readout, which corresponding to 2 16-word blocks in the L1 pipeline buffer. Data from 16 channels are grouped together, taking 1.2us to transfer from the L1 pipeline buffer to the EV buffer. Data of 48 channels are transferred in 3.6us. Truncating happens while storing data into EV buffer if too many channels are hot. The data for an event stored in the EV buffer contains 2 headers and 3 enders, one at the end of each 16-channel group. The total number of hits allowed in 48 channels is 123. The truncated data block is not good for experiment data, however, it contains all necessary header and enders to avoid hanging up the remaining readout system. Up to 256 16-bit words/event for 96 channels are stored in the 16MB SDRAM. A total of 32K events can be held in the SDRAM. Daisy chained 8 TDC_FE cards are readout through a 26.5Mbit/s data link to the controller. The total time to readout 8 x 16 MB is about 48.3 sec.

8. TDC With Hit Rate Limiter TDC T1 T0 DV Counter Hit Rate Limiter (7/256CK212) DVLD CLR CK212 L/S LD TDC/HRL CC[5..2] 7hits/256CK212, 7hits/1.2  s 5.8MHz CLRHITLD CLRCNT

9. Reset Timing 0123456789abcdef 01230123 01230123 CC[9..2] CC[4..3] CK106 SCLR SCLRQ SCLRCC CCQ[4..3]=CH 10 CLRHIT LD T=7 TCQ VTQ CH=0CH=1CH=2CH=3 ff00 CLRCNT

10. Trigger Timing 7F0123 CC[9..2] CC[9..3] CK106 CCQ[9..3] FF00 CLRCNT FE01 7F01237E TM1us MGQ[] WBK[2..0]BK1BK1+1, BK1+4 TM1us EVPRQ[7..3],[2..0]N,7N+1,0 Trig TrigReq N+1,7 N,7N+1,0 EVPR4Q[7..3],[2..0] PUSHOK=!EVPR5Q[2] 7F01237E CC3Q[9..3] (7F)(0)(1)(2)(7E) TMQQ[] (7F)(0)(1)(7E)(7F) N+1,3N,7N+1,0EVPR5Q[7..3],[2..0]

11. TDC Data Concentration L1 Buffer 1xM4K 16x256 7hits/CH/1.2  s 28hits/4CH/1.2  s 1hit: 16bits Buffer Length: (256/32)x1.2  s=9.6  s Zero Supp. TDC/HRL EV Buffer 4xM4K 16x512x2 SDRAM 16x6M/spill 12MB/spill EV Window 2 x 1.2  s 448hits/32CH/EV Buffer Input Time: 448CK106=224RF =4.2  s SDRAM WR Time: 448RF<9.6  s TDC/HRL L1 Buffer 1xM4K 16x256 Zero Supp. L1 Buffer 1xM4K 16x256 L1 Buffer 1xM4K 16x256

12. L1 Buffer 1xM4K 16x256 Zero Supp. L1 Buffer 1xM4K 16x256 Zero Supp. CCQ[13..10] WA0x[4..0] VTQ0x 0 WA1x[4..0] VTQ1x CCP1Q[12..10], CCQ[7..3] CCMLQ[12..10], CCQ[7..3] CCQ[8]=1 0 CCP1Q[12..10], CCQ[7..3] CCMLQ[12..10], CCQ[7..3] CCQ[8]=0 Event Window

13. Readout Timing G0 B=0 G4 B=0 G0 B=0 G4 B=0 G0 B=1 G4 B=1 G0 B=1 G4 B=1 G8 B=0 G12 B=0 G8 B=1 G12 B=1 G16 B=0 G20 B=0 G16 B=1 G20 B=1 G24 B=0 G28 B=0 G24 B=1 G28 B=1 G8 B=0 G12 B=0 G8 B=1 G12 B=1 G16 B=0 G20 B=0 G16 B=1 G20 B=1 G24 B=0 G28 B=0 G24 B=1 G28 B=1 0123456 1 2 1 6.6us 1.2us 0 12 3 7 65 4 34567 00 WR RD

14. Useful Numbers RF53.102MHz, 18.8ns CK212212.4MHz, 4.708ns LSB1.18ns Hit Rate Limiter Setting7hits/256CK2127hits/64RF 7hits/1.2  s, 5.8MHz Double Hit Min. Separation8xCK106, 75.5ns Event Window 2 x 1.2  s Absolute Maximum Hits/event/32ch448hits448 x 2Bytes Event Interval>512RF >9.64  s SDRAM port data rate53MHz x 2Bytes512 x 2Bytes Number of events/spill12K Absolute Maximum data/spill/FE card5.37M hits10.75MB Absolute Maximum data/spill/8 FE86MB860Mbits Readout Chain Data Rate26.5Mbits/s Absolute Maximum Spill Readout Time32.5sec

15. Data Format D/H =1 1514131211109876543210 CH[4..0]CC[9..2]T1T0 256 x CK212 = 1.2  s 1024 x 1.18 ns BD[2..0]CNT[8..0]001 EV[13..0]=1, 2,.. 16K-1 TS[9..0] 0 01 0010 0110Reserved Header/Trailer PR[1..0]

16. Zero Suppression L1 Buffer M4K 9x512 Zero Supp. TDC/HRL DV CH1 CH0 CC5 CC4 CC3 CC2 T1 T0 0 0 0 X X X X X X 1 CH1 CH0 T1 T0 DataRoll-over Marker 1/16CK212 1/4RF Counter CH[3..0] CK212 A==0 PUSH DV CC5 CC4 CC3 CC2

17. L1 Buffer Contents 0 0 0 X X X X X X 1 CH1 CH0 T1 T0 TS=n 0 0 0 X X X X X X 1 CH1 CH0 T1 T0 1 0 0 T1 T0 0 0 0 X X X X X X n+1 0 0 0 X X X X X X n+2n+4n+3 CC5 CC4 CC3 CC2 CC5 CC4 CC3 CC2 CC5 CC4 CC3 CC2

18. Hold-Shift Timing TDC T1 T0 DV Counter Hit Rate Limiter (8/256CK212) DVLD CLR CK212 L/S LD13 CC[5..2] SCLRTCQ 01 SCLRQQ CC[] SCLRTCQ LD53 Counter CH[3..0] A==0 PUSH DV PUSH 1770654 23456789abcdef01234ef0 32100 CH[]

19. POP Logic L1 Buffer M4K 9x512 POP Logic EV Buffer 2xM4K 16x512 DV CH1 CH0 CC3 CC2 CC1 CC0 T1 T0 (A==0) &POPQ Counter TP[11..4] CK212 Counter TS[11..0] CK212 INC TL POP L1 TS-TP>TL TPL1-TP<TW etc. TW TL: 256 RF = 4.8  s TW: 16 x 4 RF = 1.2  s S0. After Reset:No POP until TS-TP>TL S1. Before L1:Popping until TS-TP==TL S2. L1 Arrives:Stop popping, keep TPL1 S3. DLSEL:Resume popping PUSHEV if TPL1-TP<TW PUSHEV DLSEL DLSEL: 64 CK212 for each group.

20. POP Logic L1 Buffer M4K 9x512 POP Logic EV Buffer 2xM4K 16x512 DV CH1 CH0 CC3 CC2 CC1 CC0 T1 T0 (A==0) &POPQ Counter TP[11..4] CK212 Counter TS[11..0] CK212 INC TS-TP>TL TL POP DL Ctrl L1 DL Token In DL Token Out TPL1-TP<TW TW TL: 256RF = 4.8  s TW: 16x4RF = 1.2  s S0. After Reset:No POP until TS-TP>TL S1. Before L1:Popping until TS-TP==TL S2. L1 Arrives:Stop popping, keep TPL1 S3. DL Token in:Popping until TPL1-TP==TW Output DL Token, go to S1.

21. Hit Rate Limiter  CK212 +/- NE0 NE7 0 0 DV DVLD For each incoming hit, the accumulator is added by: –32 most of time –(-1) when >=224 (i.e., 7*32). For each clock cycle with no hit, the accumulator counts down by: –1 most of time –0 if the accumulator is empty. Long term dead-time-free hit rate: –< 1/33*212MHz = 6.4 MHz. Instantaneous dead-time-free hit rate: –< 6hit in any 256+6 time window. Absolute maximum number of hits in any 256 cycle (1.2  s): –15 hits