1. Invitation to Computer Science 6 th Edition Chapter 5 Computer Systems Organization

2. Invitation to Computer Science, 6th Edition2 Objectives In this chapter, you will learn about: The components of a computer system The Von Neumann architecture Non-Von Neumann architectures

3. Introduction Computer organization –Branch of computer science that studies computers in terms of their major functional units and how they work –Computer organization examines the computer as a collection of interacting “functional units” –Functional units may be built out of the circuits already studied Invitation to Computer Science, 6th Edition33

4. Introduction Concept of abstraction –Used throughout computer science –Without it, it would be virtually impossible to study computer design or any other large, complex system –Higher level of abstraction assists in understanding by reducing complexity Invitation to Computer Science, 6th Edition44

5. 5 Figure 5.1 The Concept of Abstraction

6. Invitation to Computer Science, 6th Edition66 The Components of a Computer System Von Neumann architecture is based on the following three characteristics –four functional units Memory Input/Output Arithmetic/Logic unit (ALU) Control unit –The stored program concept –The sequential execution of instructions

7. Invitation to Computer Science, 6th Edition7 Figure 5.2 Components of the Von Neumann Architecture

8. Invitation to Computer Science, 6th Edition8 Memory and Cache Memory –Functional unit of a computer that stores and retrieves the instructions and the data being executed –Random access memory maps addresses to memory locations –Cache memory keeps values currently in use in faster memory to speed access times

9. Invitation to Computer Science, 6th Edition9 Memory and Cache Random access (RAM) –Access technique used by computer memory –Memory made of addressable cells –Current standard cell size is 8 bits –All memory cells accessed in equal time –Memory address Unsigned binary number N long Address space is then 2 N cells Read-only memory (ROM) –Information is prerecorded during manufacture

10. Invitation to Computer Science, 6th Edition10 Memory and Cache (continued) With a cell size of 8 bits: –The largest unsigned integer value that can be stored in a single cell is 11111111 (255) [0.. (2 N – 1)] –Range of addresses available on a computer –decoder circuit When dealing with memory: –Distinguish between an address and the contents of that address

11. Invitation to Computer Science, 6th Edition11 Figure 5.5 Organization of Memory and the Decoding Logic

12. Invitation to Computer Science, 6th Edition12 Figure 5.4 Maximum Memory Sizes

13. Invitation to Computer Science, 6th Edition13 Memory and Cache (continued) Basic memory operations –Fetching and storing –Fetch: Retrieve a value from memory –Store: Store a value into memory Memory registers –Used to implement the fetch and store operations Memory Data Register (MDR) –Contains data value being fetched or stored Memory Address Register (MAR) –Holds the address of the cell to be fetched or stored

14. Invitation to Computer Science, 6th Edition14 Figure 5.3 Structure of Random Access Memory

15. Invitation to Computer Science, 6th Edition15 Memory and Cache (continued) Fetch operation –The address of the desired memory cell is moved into the MAR –Fetch/store controller signals a fetch, accessing the memory cell –The value at the MAR’s location flows into the MDR

16. Invitation to Computer Science, 6th Edition16 Memory and Cache (continued) Store operation –The address of the cell where the value should go is placed in the MAR –The new value is placed in the MDR –Fetch/store controller signals a store, copying the MDR’s value into the desired cell

17. Invitation to Computer Science, 6th Edition17 Memory and Cache (continued) Two-dimensional structure –Memory organization Memory locations –Stored in row major order Selection lines –Row selection line –Column selection line

18. Invitation to Computer Science, 6th Edition18 Figure 5.6 Two-Dimensional Memory Address Organization

19. Invitation to Computer Science, 6th Edition19 Figure 5.7 Overall RAM Organization

20. Invitation to Computer Science, 6th Edition20 Memory and Cache (continued) Fetch/store controller –Determines whether we put contents of a memory cell into the MDR or put the contents of the MDR into a memory cell Memory access time –Typically about 5 to 10 nsec

21. Invitation to Computer Science, 6th Edition21 Memory and Cache (continued) Cache memory –Principle of Locality: when the computer uses something, it will probably use it again very soon, and it will probably use the “neighbors” of this item very soon –Memory access is much slower than processing time –Faster memory is too expensive to use for all memory cells –Small size, fast memory just for values currently in use speeds computing time –Hit rate, average access time

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24. Invitation to Computer Science, 6th Edition24 Input/Output and Mass Storage Input/output (I/O) units –Devices that allow a computer system to communicate and interact with the outside world as well as store information Human interfaces: Monitor, keyboard, mouse External devices vary tremendously from each other Archival storage: Not dependent on constant power

25. Invitation to Computer Science, 6th Edition25 Input/Output and Mass Storage (continued) Input/output devices come in two basic types –Those that represent information in human- readable form for human consumption –Those that store information in machine-readable form for access by a computer system, mass storage

26. Invitation to Computer Science, 6th Edition26 Input/Output and Mass Storage Volatile memory –Information disappears when power is turned off –Example: RAM Nonvolatile storage –Information does not disappear when the power is turned off –Role of mass storage devices such as disks and tapes

27. Invitation to Computer Science, 6th Edition27 Input/Output and Mass Storage (continued) Mass storage devices –Direct access storage device Hard drive, CD-ROM, DVD Uses its own addressing scheme to access data –Sequential access storage device Tape drive Stores data sequentially Used for backup storage these days

28. Invitation to Computer Science, 6th Edition28 Input/Output and Mass Storage (continued) Direct access storage devices –Data stored on a spinning disk –Disk divided into concentric rings (sectors, stores information) –Read/write head moves from one ring to another while disk spins –Access time depends on Time to move head to correct sector Time for sector to spin to data location –Fixed number of sectors are placed in a concentric circle on the surface of the disk, called a track

29. Invitation to Computer Science, 6th Edition29 Figure 5.8 Overall Organization of a Typical Disk One surface

30. Invitation to Computer Science, 6th Edition30 Input/Output and Mass Storage (continued) Seek time –Time needed to position the read/write head over the correct track Latency –Time for the beginning of the desired sector to rotate under the read/write head Transfer time –Time for the entire sector to pass under the read/write head and have its contents read into or written from memory

31. Invitation to Computer Science, 6th Edition31 Input/Output and Mass Storage (continued) Given: –Rotation speed = 7,200 rev/min=120 rev/sec = 8.33 msec/rev –Arm movement time = 0.02 msec to move to an adjacent track –On average, the read/write head must move about 300 tracks –Number of tracks/surface = 1,000 –Number of sectors/track = 64 –Number of bytes/sector = 1,024 Seek time –Best case = 0 msec; –Worst case = 999*0.02=19.98 msec –Average case = 300*0.02 = 6 msec

32. Invitation to Computer Science, 6th Edition32 Input/Output and Mass Storage (continued) Given: –Rotation speed = 7,200 rev/min=120 rev/sec = 8.33 msec/rev –Arm movement time = 0.02 msec to move to an adjacent track –On average, the read/write head must move about 300 tracks –Number of tracks/surface = 1,000 –Number of sectors/track = 64 –Number of bytes/sector = 1,024 Latency –Best case = 0 msec; –Worst case = 8.33 msec –Average case = 4.17 msec

33. Invitation to Computer Science, 6th Edition33 Input/Output and Mass Storage (continued) Given: –Rotation speed = 7,200 rev/min=120 rev/sec = 8.33 msec/rev –Arm movement time = 0.02 msec to move to an adjacent track –On average, the read/write head must move about 300 tracks –Number of tracks/surface = 1,000 –Number of sectors/track = 64 –Number of bytes/sector = 1,024 Transfer time –1/64 * 8.33 msec = 4.17 msec

34. Invitation to Computer Science, 6th Edition34 Input/Output and Mass Storage (continued) BestWorstAverage Seek Time019.886 Latency08.334.17 Transfer0.13 Total0.1328.4410.3

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37. Invitation to Computer Science, 6th Edition37 Input/Output and Mass Storage (continued) Sequential access storage device (SASD) –Does not require that all units of data be identifiable via unique addresses Direct access storage devices –Much faster at accessing individual pieces of information

38. Invitation to Computer Science, 6th Edition38 Input/Output and Mass Storage (continued) I/O controller –Has small amount of memory (I/O buffer) –I/O control and logic: ability to handle mechanical functions of the I/O device –Intermediary between central processor and I/O devices –Processor sends request and data, then goes on with its work –I/O controller interrupts processor when request is complete

39. Invitation to Computer Science, 6th Edition39 Figure 5.9 Organization of an I/O Controller

40. Invitation to Computer Science, 6th Edition40 The Arithmetic/Logic Unit Subsystem that performs addition, subtraction, and comparison for equality Components –Registers, interconnections between components, and the ALU circuitry Register –Storage cell that holds the operands of an arithmetic operation and holds its result Bus –Path for electrical signals

41. Invitation to Computer Science, 6th Edition41 The Arithmetic/Logic Unit Registers are similar to RAM with following minor differences –They do not have a numeric memory address but are accessed by a special register designator such as A, X or R0 –They can be accessed much more quickly than regular memory cells –They are not used for general purpose storage but for specific purposes such as holding the operands for an upcoming arithmetic computations. A typical ALU has 16, 32 or 64 registers.

42. Invitation to Computer Science, 6th Edition42 Figure 5.10 Three-Register ALU Organization

43. Invitation to Computer Science, 6th Edition43 Figure 5.11 Multiregister ALU Organization

44. The Design Philosophy behind ALU The design philosophy behind an ALU is not to have it perform only the correct operation. Instead, it is to have every ALU circuit “do its thing” but then keep only the one desired answer. Invitation to Computer Science, 6th Edition44

45. Invitation to Computer Science, 6th Edition45 Figure 5.12 Using a Multiplexor Circuit to Select the Proper ALU Result

46. Invitation to Computer Science, 6th Edition46 Figure 5.13 Overall ALU Organization

47. Invitation to Computer Science, 6th Edition47 The Control Unit Stored program –The fundamental characteristics of the VON Neumann architecture –Sequence of machine language instructions stored as binary values in memory Control unit –Tasks: fetch, decode, and execute

48. The Control Unit Fetch: get from memory the next instruction to be executed Decode: determine what is to be done Execute: issue the appropriate command to the ALU, memory or I/O controllers. These three steps are repeated over and over until we reach the last instruction in the program, typically something called HALT, STOP, or QUIT. To understand, control unit, first the characteristics of machine language instructions need to be learned Invitation to Computer Science, 6th Edition48

49. Invitation to Computer Science, 6th Edition49 Machine Language Instructions Instructions that can be decoded and executed by the control unit of a computer Operation code field –Unique unsigned integer code assigned to each machine language operation recognized by the hardware Address field(s) –Memory addresses of values on which the operation will work

50. Invitation to Computer Science, 6th Edition50 Figure 5.14 Typical Machine Language Instruction Format

51. Invitation to Computer Science, 6th Edition51 Machine Language Instructions (continued) Instruction set –Set of all operations that can be executed by a processor Classes of machine language instructions –Data transfer –Arithmetic –Compare –Branch

52. Invitation to Computer Science, 6th Edition52 Machine Language Instructions (continued) Data transfer instructions –LOAD X – Load register R with the contents of memory cell X. –STORE X – Store the content of register R into memory cell X. –MOVE X, Y – Copy the contents of memory cell X into memory cell Y

53. Machine Language Instructions (continued) Arithmetic/logic operations –Perform ALU operations that produce numeric values Example: ADD X, Y, Z (Three – address instruction) CON(Z) = CON(X) + CON(Y) ADD X, Y (Two – address instruction) CON(Y) = CON(X) + CON(Y) ADD X (One – address instruction) R = CON(X) + R Invitation to Computer Science, 6th Edition53

54. Machine Language Instructions (continued) Compare operations –Compare two values and set an indicator on the basis of the results of the compare; set status register (or we call condition register, special register) bits Eg: COMPARE X, Y –CON(X) > CON(Y) set GT = 1, EQ = 0, LT = 0 –CON(X) = CON(Y) set GT = 0, EQ = 1, LT = 0 –CON(X) < CON(Y) set GT = 0, EQ = 0, LT = 1 Invitation to Computer Science, 6th Edition54

55. Machine Language Instructions (continued) Branch operations –Jump to a new memory address to continue processing Eg: –JUMP X (unconditionally) –JUMPGT X / JUMPEQ X / JUMPLT X –JUMPGE X / JUMPLE X –HALT Invitation to Computer Science, 6th Edition55

56. Machine Language Instructions (continued) Reduced instruction set computers or RISC machines –Include as little as 30–50 instructions Complex instruction set computers (CISC machines) –Include 300–500 very powerful instructions Invitation to Computer Science, 6th Edition56

57. Invitation to Computer Science, 6th Edition57 Control Unit Registers and Circuits Control unit depends on following two registers to fetch and execute instructions: Program counter (PC) –Holds the address of the next instruction to be executed Instruction register (IR) –Holds a copy of the instruction fetched from memory Instruction decoder –Determines what instruction is in the IR

58. Invitation to Computer Science, 6th Edition58 Figure 5.16 Organization of the Control Unit Registers and Circuits

59. Invitation to Computer Science, 6th Edition59 Figure 5.17 The Instruction Decoder

60. Invitation to Computer Science, 6th Edition60 Figure 5.15 Examples of Simple Machine Language Instruction Sequences

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63. Invitation to Computer Science, 6th Edition63 Putting All the Pieces Together–the Von Neumann Architecture Program execution phases –Fetch, decode, and execute Von Neumann cycle –The repetition of the fetch/decode/execute phase

64. Invitation to Computer Science, 6th Edition64 Figure 5.18 The Organization of a Von Neumann Computer

65. Invitation to Computer Science, 6th Edition65 Figure 5.19 Instruction Set for Our Von Neumann Machine

66. Invitation to Computer Science, 6th Edition66 Non-Von Neumann Architectures Problems that computers are being asked to solve –Have grown significantly in size and complexity Important limit on increased processor speed –Inability to place gates close together on a chip (50- 100 nanometers) Slowing down –Rate of increase in performance of newer machines Von Neumann bottleneck –Inability of the sequential one-instruction-at-a-time Von Neumann model to handle today’s large-scale problems

67. Invitation to Computer Science, 6th Edition67 Figure 5.20 Graph of Processor Speeds, 1945 to the Present

68. Non-Von Neumann Architectures (continued) Parallel processing –Building computers not with one processor, but with tens, hundreds, or even thousands SIMD parallel processing (vectors) –ALU is replicated many times –Each ALU has its own local memory where it may keep private data MIMD parallel processing (subtasks) –All processors are replicated –Every processor is capable of executing its own separate program Invitation to Computer Science, 6th Edition68

69. Invitation to Computer Science, 6th Edition69 Figure 5.21 A SIMD Parallel Processing System

70. Invitation to Computer Science, 6th Edition70 Non-Von Neumann Architectures (continued) Scalability –It is possible to match the number of processors to the size of the problem Massively parallel MIMD machines –Have achieved solutions to large problems thousands of times faster than is possible using a single processor Grid computing –Enables researchers to easily and transparently access computer facilities without regard for their location –SETI@home project, analyze radio telescope data

71. Invitation to Computer Science, 6th Edition71 Summary of Level 2 Chapter 4 –Looked at the basic building blocks of computers: binary codes, transistors, gates, and circuits Chapter 5 –Examined the standard model for computer design, called the Von Neumann architecture System software –Intermediary between the user and the hardware components of the Von Neumann machine

72. Summary Computer organization –Examines different subsystems of a computer: memory, input/output, arithmetic/logic unit, and control unit Machine language –Gives codes for each primitive instruction the computer can perform and its arguments Von Neumann machine –Sequential execution of a stored program Parallel computers –Improve speed by doing multiple tasks at one time Invitation to Computer Science, 6th Edition72

73. Email the group member information to CSC2010ITCS@gmail.com Subject: Group Body: names of team members 2-4, individual Mar 27 th Invitation to Computer Science, 6th Edition73