1. Other Logic Implementations

2. Pass gate/Transmission Gate
C=1
OUT=A
C=0
OUT=NO OUTPUT (OPEN CIRCUIT)
Pass Gate
NMOS passes good logic ‘0’
PMOS passes good logic ‘1’
CMOS TRANSMISSION GATE (TG)

3. Multiplexer
C=1
C=0 1 A 1 B C A B F 1

4. AND Gate
A=1 B=1 1 1 1 1 A B F 1 1
A=0 B=1 1 1 1

5. OR Gate
A=0
B=0 1 1 A B F 1
A=1
B=0 1 1 1

6. Delay Calculations of Pass gates

7. 4-1 MUX

8. High Current Delivery For High Current requirements of L-H transitions
For High Current requirements of H-L transitions

9. Tristate 1
0/1 Z
0/1
1/0 1 EN IN
OUT 1 X

10. EX-OR Gate A B F 1

11. EX_OR
A=1
B=1 X 1 1
A=1 B=0 1 1
A=1 B=1
A=0
B=1 1 1 1 1 1 1

12. EX-OR/NOR With Driving Output
A=0
B=0 10 1
An inversion of the left circuits
A=0
B=1 1 1 X X 1

13. PLA

14. Example : PLA

15. Transistor level Implementation
Input Lines
Output line
Input Lines
Output Lines

16. Pseudo-nMOS Implementation
Red is Input
Green is Ground
Ground

17. Altera 40nm FPGA’a http://www. altera
Table 2. HardCopy IV E Devices Overview
Device (1)
ASIC Gates (2)
Memory Bits (3)
I/O Pins
PLLs
FPGA Prototype
HC4E2YZ
3.9M
8.1 4
EP4SE110
HC4E3YZ
9.2M
10.7
EP4SE230
HC4E4YZ
7.6M
4/8/12
EP4SE290
HC4E5YZ
9.5M
16.8
EP4SE360
HC4E6YZ
11.5M
8/12
EP4SE530
HC4E7YZ
13.3M
EP4SE680
Notes:
Y = I/O count, Z = package type (see the product catalog for more information)
ASIC gates calculated as 12 gates per logic element (LE), 5,000 gates per 18 x 18 multiplier (SRAMs, PLLs, test circuitry, I/O registers not included in gate count)
Not including MLABs

18. FPGA Comparison Table Features Artix-7 Kintex-7 Virtex-7 Spartan-6
Logic Cells
352,000
480,000
2,000,000
150,000
760,000
BlockRAM
19Mb
34Mb
68Mb
4.8Mb
38Mb
DSP Slices
1,040
1,920
3,600
180
2,016
DSP Performance (symmetric FIR)
1,248GMACS
2,845GMACS
5,335GMACS
140GMACS
2,419GMACS
Transceiver Count 16 32 96 8 72
Transceiver Speed
6.6Gb/s
12.5Gb/s
28.05Gb/s
3.2Gb/s
11.18Gb/s
Total Transceiver Bandwidth (full duplex)
211Gb/s
800Gb/s
2,784Gb/s
50Gb/s
536Gb/s
Memory Interface (DDR3)
1,066Mb/s
1,866Mb/s
800Mb/s
PCI Express® Interface
Gen2x4
Gen2x8
Gen3x8
Gen1x1
Agile Mixed Signal (AMS)/XADC
Yes
Configuration AES
I/O Pins
600
500
1,200
576
I/O Voltage
1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V
1.2V, 1.5V, 1.8V, 2.5V, 3.3V
1.2V, 1.5V, 1.8V, 2.5V
EasyPath Cost Reduction Solution -

19. use a narrow clock pulse. (Impractical)
Sequential Circuits
For correct operation,
Solution:
use a narrow clock pulse. (Impractical)

20. Clocking Conditions Condition to achieve proper operation:
Problem: Clock Skew

21. Two-phase Non-Overlapping clocking
Problems:
Routing two Clock Nets,
Lower Frequency of
Operation

22. Sequential Circuits-Single Clock
-ve going edge
Single clock to synchronize operations
Suitable for simple applications

23. Different Latches Static latch with cross-coupled circuit Dynamic
Static latch with clocked feedback
Buffered static latch with clocked feedback

24. D-Latch and the Flip Flop Operations

25. The Master Slave Flip Flop
+ve edge of CLK 2

26. Master Slave Flip Flop Setup time=G4+G5+G6 Hold time=G1+G2 W1=G5+G6+G3
Cycle time=W1+W2
CLK generated locally
Typical arrangement,

27. Set-Up Time G4+G5+G6 Before CP Active Edge 0 11 X
Before
CP Active Edge
Data has to bet set stable
Set-Up Time
G4+G5+G6

28. Hold Time G1+G2 After CP Active Edge 1 0 Data has to bet set stable XX 1 1
Hold Time
G1+G2 1 X 1 1

29. 1 X
LOW VALUE, W2
G3 +G5 +G6

30. 1 X
CLK HIGH , W1
G7 +G9 +G10

31. CMOS two phase double latch circuits
Dynamic
CLK1=1
CLK2=1
CLK1=1
CLK2=1
Static un-buffered
Static buffered

32. Edge Triggered, D Flip Flop
NAND1 S Q
NAND2
NAND5
clk R
NAND3
NAND6 D
NAND4
reset

33. When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3
reset Q
NAND1
NAND2
NAND3
NAND4
NAND5
NAND6 S R
Path for set up
Path for hold
Nand00 1
01 1 1
0 1

34. When CLK changes from 0 to 1 Case2, D=1 tsetup=t4 + t1 thold= t2
reset Q
NAND1
NAND2
NAND3
NAND4
NAND5
NAND6 S R
Path to hold 1
Nand00 1
01 1
0 1
Path to set up

35. When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3
Case2, D=1 tsetup=t4 + t1 thold= t2
clk D
reset Q
NAND1
NAND2
NAND3
NAND4
NAND5
NAND6 S R

36. D Flip Flop
Rising Edge
Data Change

37. D Flip-Flop with direct set and clear
Input
Output SD CD D C O O’ H L X
On+1
O’n+1

38. JK Flip-Flop Input Output SD CD C J K O O’ H L X On+1 O’n+1 No Change

39. Thank you !