1. DSP C5000 Chapter 13 Numerical Issues Copyright © 2003 Texas Instruments. All rights reserved.

2. ESIEE, Slide 2 Learning Objectives  Data formats Data formats Data formats  Fixed point: integer and fractional numbers Fixed point Fixed point  Use methods for handling multiplicative and accumulative overflow  Floating point Floating point Floating point  Block floating point Block floating point Block floating point  Comparison of formats

3. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 3 Data Formats and Numerical Issues  Common data sizes: 8, 16, 24, 32 bits  Fixed or floating point  For a given technology:  Fixed point is faster and less expensive  But fixed point programming is more difficult  Processors of the ‘C5000 family are fixed point processors.  But they can also execute floating point operations through software

4. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 4 Digital Representation of a Signal  Sampling  ADC Analog to Digital Conversion  Quantization  Coding of the quantized value  Digital representation used in DSP

5. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 5 Digital Coding of Data and Arithmetic  Finite precision:  Representation uses a given number of bits  Fixed point  Floating point  Block floating point

6. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 6 Interface ADC - DSP - DAC ADCADC DSPDSP DACDAC Possible Conversions: fixed point floating point A or mu law linear law (Compression-Expansion)

7. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 7 Binary Representation of Signed Integers used in ADC-DAC or DSP in Fixed Point Format  2’s Complement (digital processors)  1’s Complement  Sign, magnitude  Offset Binary

8. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 8 Fixed Point Arithmetic 2’s Complement Representation

9. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 9 Example of Size 3 bits for Integers, Decimal and Binary Representations

10. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 10 Example of Size 3 bits for Integers, Decimal and Binary Representations

11. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 11 Representation of Signed Integers in 2’s Complement Format

12. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 12  Format Qk : k fractional bits associated with negative power of 2.  The binary representation of a number x in format Qk is the 2’s complement representation of the integer y: Non-Integer Numbers Using Fixed Point

13. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 13 Some Properties of 2’s Complement Representation Related status bits in C5000 DSP OVM = OVerflow Mode of the C54 DSPs on C54 DSPs SATD = SATuration mode of the D unit on C55 DSPs SXM = Sign eXtension Mode on C54 DSPs SXMD = Sign eXtension Mode of the D unit on C55 DSPs

14. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 14 Addition and Subtraction Using 2’s Complement  Simple hardware operator: to add 2 signed N-bit integers with a result of size N bits. Whatever the sign of numbers, it is sufficient to add the 2’s complement values. 1 2 3 -4 -3 -2 0 OV=1 Carry 111 + 111 -------- 1 110 010 + 001 -------- 0 011 110 + 011 -------- 1 001 110 + 001 -------- 0 111 Overflow (intermediate)

15. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 15 Multiplying and Shifting in 2’s Complement  Simple hardware operator but more difficult than with a sign-magnitude representation.  The product of 2 N-bit numbers needs support for 2N-bit results.  Generally, the product register is of size 2N bits => 2 identical MSB (1bit left shift).  Booth Algorithm (on 3 bits) AB=-4A(b2-b1)-2A(b1-b0)-A(b0-0)  k bits right Arithmetic shifting: sign bit extension necessary.

16. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 16 Sign eXtension Mode SXM or SXMD  With 2’s complement, when 16-bit data are loaded into a 32-bit accumulator, the sign bit is also extended.  This sign extension may be annoying: e.g. Calculation of 16-bit addresses.  The user can choose whether or not to use sign bit extension mode.  SXM = Sign eXtension Mode bit in the status word ST1 in C54 DSPs.  SXMD = Sign eXtension Mode bit for the D unit in the status word ST1_55 in C55 DSPs

17. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 17 Sign Bit Extension  Example data size 6 bits, Accumulator size 12 bits 1 0 1 0 0 1 1 1 1 0 0 0 Data Loading of ACCU with sign extension Loading of ACCU without sign extension

18. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 18 Addition Overflow  When adding 2 numbers of size N bits, the result may need N+1 bits.  Example for integers of N=3 bits:  3+3 = 6 cannot be represented using 3 bits, but can be expressed using 4 bits.  In format Q2 of N=3 bits, 0.75 + 0.5 =1.25 cannot be represented using 3 bits, needs 4 bits.  When adding M numbers of N bits, the result potentially needs N+ log2(M) bits.

19. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 19 Using Saturation  Overflows in 2’s complement create unexpected sign changes and peaks that are difficult to filter.  Saturation arithmetic detects the overflow and replaces the result with a saturation value. 00.20.40.60.81 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Saturation at 0.75 2’s complement overflow Example, max value = 0.75

20. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 20 Setting saturation modes with OVM or SATD  The user can choose whether or not to use saturation mode by setting the corresponding mode bits.  OVM = OVerflow Mode bit in status word ST1 in C54 DSPs.  If OVM = 1:  positive results are saturated to 00 7FFF FFFF  Negative results are saturated to FF 8000 0000.  SATD = SATuration mode bit for the D unit in the status word ST1_55 in C55 DSPs.  If SATD = 1 and M40 =0, same as for C54 DSP  If SATD=1 and M40 =1  positive results are saturated to 7F FFFF FFFF  Negative results are saturated to 80 0000 0000.

21. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 21 Saturation mode for the A unit in C55 DSPs  SATA = SATuration mode bit for the A- unit ALU in the status word ST3_55 in C55 DSPs.  If SATA=1, if a calculation in the A-unit results in an overflow:  positive results are saturated to 7FFF  Negative results are saturated to 8000.

22. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 22 Effect of 2’s Complement Overflow  As 2’s complement is a circular representation, if the result holds on N bits, the intermediate overflows do not alter the final result  This is not the case for saturation  Example of N = 3 bits:  Calculate x = 3+2-4, the theoretical result is 1  With 2’s complement overflow:  Calculate first y=(3+2)= 011+010 =101 =-3 overflow  Then (y-4)=101+100=1 001 = 1 and carry =1 correct result  With saturation:  Calculate first y=(3+2)=3 saturation  Then (y-4) = 011+100=111=-1 wrong result  If a system has a unity gain, saturation should not be used.

23. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 23 Example of 2’s Complement Binary Representations  Represent x = 1.75 using N=6 bits in format Q3  Answer 001.110 = 1 +1/2 +1/4  Represent x = -1.75 using N=6 bits in format Q3  Answer 110.0 10 = - 4 +2+1/4  Represent x = 1. 805 using N=6 bits in format Q3  Answer 001.110 = 1 + 1/2 + 1/4

24. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 24 Operations with Fractional Numbers using Fixed Point Format  Addition: align on same size N and align bits with same weight.  Multiplication: product requires 2N bits

25. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 25 Example of 2’s Complement Binary Operations  Data size N=6, format Q3  Product 12 bits, Q6  Product 1.75 x 2.5 = 4.375  Binary representation:  001.110 x 010.010 = 000100.011000  Sum 6 bits, format Q3  Sum 1.75 + 1.5 = 3.25  Binary representation:  001.110 + 001.100 = 011.010

26. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 26 Accumulator and size of the result  The final result of a calculation usually uses more than 16 bits (size of memory words).  ACCUs use 32, 40, 56... Bits  If we want to save the result in a single memory word, the question is:  Which pack of N bits must be saved from accumulator?  Possibility of overflow and underflow  Overflow during accumulation or during saving.

27. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 27ACCUMULATOR  Possibility of overflow and underflow  Scaling when adding many products

28. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 28 Saturation on store mode, SST bit  SST = mode bit in PMST (C54) or ST3_55 (C55) status word.  If SST is set, the CPU saturates a shifted or unshifted accumulator value before storing it.  The saturation value depends on the value of the sign extension mode bit.  ACCU remains unchanged.

29. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 29 Example of Fixed Point Processing y(n)=x(n)+a 1 y(n-1)  Data size N=16, product size 32 bits, accumulator size 40 bits  The coefficient a 1 is smaller than 1: format Q15. Format of data = Q15, accumulator size 40bits Accumulator

30. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 30 Representation of Sum of Products  The basic sum of M products operation, for data and coefficients of size N bits:  Needs 2N bits for each product + log2(M) bits for the sum of M products, or maximum 2N+log2(M) bits.  The C5000 DSP has Accumulators of size 32+8 bits that allow for the sum of 256 products without overflow.  If M>256, may necessitate scaling of data

31. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 31 Solutions to Overflow  Overflow multiplication can be prevented by using pure fractional numbers (< 1)  Saturation of the result  Scaling of the inputs and use of fractional arithmetic  But loss of precision  Use double precision or double word  But decreases speed of calculation  Use DSP with larger accumulators.  8 guard bits in the’C5000 accumulators.  Design system with unity gain.  Use floating point

32. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 32 Products of size 2N or 2N-1 Bits? 1 of 3  The product of 2 data values of size N bits can be stored using 2N-1 bits, except where the two most negative numbers are multiplied together.  Example of size N=3 bits for integer values.  The integer values are between –4 and +3.  All the products are between –16 and +15 and can be written on 2N-1=5 bits,  Except –4 x –4 = 16.  Example on N=16 bits and Q15 format:  -1 x –1 = +1 cannot be written on 31 bits in Q30.

33. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 33 Products of Size 2N or 2N-1 Bits? 2 of 3  Consider the case of data < 1 using N=16 bits, Q15 format.  Their products are < 1 and can be expressed using 32 bits format Q30 with 2 sign bits  It is possible with the C5000 DSP to automatically eliminate one sign bit by a left shift of 1 bit, thus obtaining a Q31 result.  If bit FRCT in ST1 is set to 1, products are automatically shifted left by 1 bit.

34. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 34 Products of Size 2N or 2N-1 Bits? 3 of 3  The exception –1 x –1 can be treated using the SMUL status bit that saturate the result of the multiplication before accumulation. –1 is equal to 8000 in hexadecimal on 16 bits.  If SMUL=1, SATD or OVM=1, FRCT =1  The product of (1)8000 x (1)8000 is saturated to the positive number 7FFF FFFF after the multiplication and before accumulation in MAC or MAS instructions.  Consistent with ETSI-GSM specifications.

35. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 35 Fixed Point Programming  Perpetual compromise between dynamic range and precision constraints  Keep enough bits to represent the integer part of the result  Keep enough bits in the fractional part to satisfy the precision.  Rounding results.

36. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 36 Entering Non-Integer Values using the Software Development Tools  The tools do not support fractions  To store 0.707 in Q15 use: .word 32768*707/1000  To store 3.252 in Q13 use: .word 8192*3252/1000  Generally, to convert a real number x using 2’s complement representation with size N bits and format Qk:  Calculate the integer y=round(x 2 k )  The 2’s comp. representation of y is the 2’s comp. representation of x in format Qk.

37. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 37 Some more stuff on Saturation 0 1 128 -128AC0 SAT AC0 Two saturation methods exist:  Manual: using the SAT instruction (ACx only)  Auto: using the SATA/SATD or OVM control bits SATA affects TAx registers (T0-3/AR0-7) in A unit SATA affects TAx registers (T0-3/AR0-7) in A unit ex: 7FFFh + 2 = 7FFFh ex: 8001h - 3 = 8000h SATD affects AC0-3 registers in D unit SATD affects AC0-3 registers in D unit (ST1_55 M40 = 0) 00.7FFF.FFFF or FF.8000.0000 (ST1_55 M40 = 1) 7F.FFFF.FFFF or 80.0000.0000 - Affects ST0_55 ACxOV and can be tested

38. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 38Rounding $ 1.53 $ 0.50 $ 2.03 $ 2. How do you round this amount to the nearest $ ? - Add $0.50  Biased Rounding (ST2_55 RDM = 0) or round to the infinite - Direct: ROUND AC0 - Store: MOV uns(rnd(HI(saturate(AC0)))),*AR1  rnd() and ROUND perform the following operation: (add 1 to bit 15) and (truncate) (ACx+0x8000) & 0xFFFF0000 - Partial result - Truncate result (to nearest $)  Instructions RND in C54 DSPs or ROUND in C55 DSPs, rounds the content of the accumulator.  For the C55, 2 kinds of rounding: biaised or unbiaised, depending on the bit RDM in ST2_55.

39. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 39 Other Useful Stuff...  Setting ST1_55 SMUL, FRCT, SATD = 1 will saturate (-1 x -1) to 7FFF_FFFFh prior to adding/subtracting to/from the accumulator. This ensures a 1 cycle ETSI-compatible operation and prevents temporary overflow. Absolute Value ABS AC0,AC1 2’s Complement NEG AC0,AC1 1’s Complement NOT AC0,AC1 1-bit division SUBC Smem,ACx Normalization MANT; EXP Copyright © 2003 Texas Instruments. All rights reserved. - 39

40. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 40 Floating Point Arithmetic

41. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 41 Floating Point Representation  Number x -> Mantissa M and Exponent E  If M is of size m bits and E is of size e bits, then x is of size N = m + e bits  Range of positive numbers for 0.5  |M| <1 and 2’s comp. representation of M and E:

42. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 42 Normalization of the mantissa  The decomposition of a real value x into the product of a mantissa and an exponent term is not unique:  x=M 1 2 E1 =M 2 2 E2 …  Example: 12.8=0.8 2 4 and also 12.8= 1.6 2 3  M must be normalized to make the decomposition unique.  The normalization is a constraint applied to M  for example: 0.5  |M| < 1  The ratio of the limits of the interval must be smaller than 2 to have the same exponent.

43. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 43 Floating Point Representation  Non-linear scale:  The precision decreases geometrically while the data size increases. 0x min 2x min 4x min 8x min values For a given number of bits: the number of bits of the mantissa determines the precision the number of bits of the exponent determines the dynamic range.

44. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 44 Floating Point Overflow or Underflow  Very unlikely to occur

45. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 45 Floating Point Addition Operator  It is necessary to denormalize the smallest number (B)  Its mantissa is multiplied by 2 Eb-Ea before being added to Ma.  Loss of precision due to the rounding of the mantissa

46. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 46 Floating Point Multiplication Operator  It is necessary to normalize M a M b  1 extra bit would be necessary to prevent overflow of E a +E b.  2m-1 bits are necessary to represent M a M b  If M is truncated to m bits, the absolute error increases rapidly.

47. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 47 Examples of Floating Point DSP  Some DSP devices of the C6000 family:  C67xx support both single and double precision format.  The C5000 DSP are fixed point DSP but can be programmed in floating point if necessary.

48. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 48 Example of Floating Point Representation  Represent x=1.75 in Floating Point  Use N=8, Mantissa size m=5 bits, exponent size e=3 bits, M and E in 2’s complement  Mantissa normalized to 0.5  |M| <1  Solution:  E=1 in binary representation: 001  M=0.875 in binary representation 0.1110

49. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 49 Comparison of Fixed and Floating Point Formats  Fixed point: linear scale  Absolute error more or less constant  SNR decreases when the input decreases  Floating point: non-linear scale with a geometrical progression  Relative error more or less constant  SNR more or less constant over the full data range

50. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 50 Quantization Error and SNR with Fixed-Point

51. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 51 Quantization Error with Floating Point

52. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 52 Quantization Error and SNR with Floating Point

53. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 53 Comparison of Fixed Point and Floating Point SNR Example for N=16 bits: m=12 e=4 Floating point SNR Fixed point SNR

54. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 54 Comparison of Fixed Point and Floating Point  For N bits, with Floating Point format there is a compromise between dynamic range (E), and precision (M).  Example for N=32 bits: Fixed Point 32 bits Dynamic Range Precision max Dynamic Range Precision Floating Point: m=24 b=8 Dynamic range is defined as the ratio of the largest positive value on the smallest non zero positive value

55. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 55 Fixed Point vs. Floating Point  Fixed Point:  Simple operators of addition and multiplication  But it is necessary to monitor overflow and underflow in order to keep precision and dynamic range at their best.  Floating Point:  Greater dynamic range and simpler programming  More complex operators, so the performances in terms of speed or power consumption are not so good as those of fixed point DSP.

56. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 56 IEEE 754 Floating Point Format 1 of 4  Most processors respect the IEEE 754 format for Floating Point representation of numbers.  IEEE format for N=32 bits: 32 bits = 1 bit (Sign bit) + 8 bits (Exponent) + 23 bits (Fraction) Exponent: offset binary, offset = 127, exponent=expo-127 Mantissa: sign-magnitude, normalized between 1.0...0 and 1.1...1 Hidden bit 1,....Only the fractional part (Fraction) is stored. When exponent not equal to 0, |Mantissa = 1.fraction e.g. : x=28=1,75 2 4  0 10000011 1100...0

57. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 57 Dynamic Range of IEEE 754 Single Precision Floating Point Format 2 of 4  Largest positive number:  Max exponent = 254-127=127  Max Mantissa = 2-2 -23  Max positive value = (2 -2 -23 )x2 127  2 128  Smallest positive number (non-zero)  Min exponent = 1-127  Min Mantissa = 1.0  Min positive value = 1.0 x 2 -126

58. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 58 IEEE 754 Single precision Floating Point Format, Special Cases 3 of 4  Zero: 32 bits are 0  Underflow: exponent < 1  Overflow: exponent > 254

59. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 59 IEEE 754 Floating Point Format 4 of 4  Double precision 64 bits:  1+11+52  Exponent offset binary: offset= 1023  Extended simple precision 43 bits: 1+11+31  Extended Double precision 79 bits: 1+15+63

60. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 60 Block Floating Point

61. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 61 Block Floating Point  This is not a DSP format  This is a way of doing floating point operations efficiently on a fixed point DSP  Natural approach for block operations such as the Fast Fourier Transform (FFT).  See details in chapter 19.

62. Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 62 Block Floating Point  A register contains the value of the exponent (constant) to be applied to a block of data: BLOCK EXPONENT  The mantissa is of size N bits.  Each data block is tested and scaled by the exponent in order to avoid overflows.  Useful when N is small (e.g.: N=16 bits)  Limits the loss of precision due to the increase in dynamic range of floating point.