1. EEL-3705 TPS QUIZZES Chapter 4

2. Quiz 4-1

3. Using the 2x4 Decoder shown below and two-input OR gates, design a logic circuit which implements

4. Solution

5. Quiz 4-2

6. Using the 3x8 Decoder shown below and two-input OR gates, design a logic circuit which implements

7. Solution

9. Quiz 4-3

10. Using the 3x8 Decoder shown below and two-input OR gates, design a logic circuit which implements

11. Solution

12. Quiz 4-4a

13. Using 3x8 Decoders with Active LOW Enables and NOT gates, design a logic circuit which implements a 4x16 decoder

14. Solution

15. Quiz 4-4b

16. Using standard two-input and three- input logic gates, design an encoder circuit that implements the following truth table abcy1y0 1d101 d1010 00d11

17. Solution 111 1

18. Y1

19. Solution 11 1 1

20. Y0

21. Quiz 4-5

22. Using standard two-input logic gates, design a 2X1 MUX which implements Your circuit should have three inputs, Data inputs D0 and D1, and control input S. Hint: Develop the truth table first

23. Solution D1D0SF d 0 D1d1

24. Solution

25. Demonstrations

26. 1 bit deep 2x1 MUX 2 Logical Data Inputs 1 bit deep 1 Control Input 1 Logical Output 1 bit deep

27. 1 bit deep 4x1 MUX 4 Logical Data Inputs 1 bit deep 2 Control Inputs 1 Logical Output 1 bit deep

28. 2 bits deep 2x1 MUX 2 Logical Data Inputs 2 bits deep 1 Control Input 1 Logical Output 2 bits deep

29. 2 bits deep 4x1 MUX 4 Logical Data Inputs 2 bits deep 2 Control Inputs 1 Logical Output 2 bits deep

30. 4 bits deep 2x1 MUX 2 Logical Data Inputs 4 bits deep 1 Control Input 1 Logical Output 4 bits deep

31. Quiz 4-6

32. Using the 2X1 MUX shown below and NOT gates, design a logic circuit which implements:

33. Solution We need We have Let a=s, D0=b, D1=b

34. Quiz 4-7

35. Using standard two-input logic gates, design a 2X1 MUX with Enable which implements Your circuit should have four inputs, Data inputs D0 and D1, and control inputs E and S.

36. Solution D1D0ESF dd0d0 d 10 D1d11

37. Solution

38. Quiz 4-8

39. Design a 4x1 MUX using the 2x1 MUX with enable shown below, NOT, and OR gates Your design should implement this equation

40. Solution

41. Quiz 4-9

42. Using the 4x1 MUX shown below and NOT gates, design a logic circuit which implements

43. Solution

44. Quiz 4-10

45. Using the 4x1 MUX shown below and NOT gates, design a logic circuit which implements

46. Solution c c c c a b F

47. Class Design Project

48. Quiz 4-11 Module A

49. Design a logic circuit (let’s call this module A) which converts a three bit signed magnitude input into its equivalent three bit two’s complement output. Let X 2 =0 indicate a positive number and X 2 =1 indicate a negative number. X 1 and X 0 represent the magnitude of the number. For example Hint: Really this is a hint !!!, Develop the truth table for all possible input combinations INPUT: X[2..0] OUTPUT: A[2..0] Module A

50. Solution X2X1X0A2A1A0 000000 001001 010010 011011 100000 101111 110110 111101

51. Solution

52. 11 1 1

53. Quiz 4-12 Module B

54. Design a logic circuit (let’s call this module B) which computes where A is a three bit two’s complement input with a domain of -3 to 3. Hint: This is really another hint!!!, Precompute B in decimal for each possible A and develop a truth table relating B to A in binary. Assume don’t care for B when |A| > 3. How many bits are you going to need for B? INPUT: A[2..0] OUTPUT: B[??..0] Module B

55. Solution A2A1A0BB3B2B1B0 0001111 00110001 01030011 01150101 100Ddddd 101-71001 110-51011 111-31101

56. Solution

57. 1 1 11

58. Quiz 4-13 Module C

59. Using Half Adders and NOT gates, design a logic circuit which will compute the 2’s comp of a 4-bit signed binary number INPUT: B[3..0] OUTPUT: C[3..0] Module C Hint: Calculate the 1’s complement and add 1.

60. Solution

61. Quiz 4-14 Module D

62. Using Module C (i.e. 2’s comp module) and the 4-bit wide 2X1 MUX shown below, design a logic circuit which will calculate the sign magnitude of a 4-bit 2’s complement number. You may assume maximum magnitude is 7. Your design should also have an output labeled sign which is sign=1 for negative values. INPUT: B[3..0] OUTPUT: D[2..0] Sign Module D

63. Solution

64. Quiz 4-15 Class Design Project

65. We have the design for four modules: A: 4-bit Sign Magnitude to 2’s complement B: y=2x-1 for |X|<4 C: 4-bit 2’s complement generator D: 4-bit 2’s complement to Sign Magnitude Team with two other groups. One group (X) should implement module A One group (Y) should implement module B One group (Z) should implement module C,D Pick your groups and decide who is X,Y, and Z.

66. I will give a series of inputs to Group X, who should compute A =A[2..0] and give it to group Y, who then needs to compute B=B[3..0] and give it to group Z who then needs to compute D=D[2..0] and Sign. Group D should convert the result to decimal using a minus sign to represent a negative number and record it on the board. Use the index card to pass data from one module to the next.

67. Block Diagram ABC/D X[2..0]A[2..0]B[3..0]D[2..0] Record Results On Board From Dr. Perry Sign

68. X=000 1

69. X=100 2

70. X=001 3

71. X=101 4

72. X=011 5

73. X=111 6

74. Quiz 4-16

75. Let tgate=15ns, calculate the worst case delay for a 32-bit adder for the three circuits below. CircuitDelay Ripple Carry (2n+1)tgate Fully Parallel 2*tgate Carry Look Ahead 4*tgate

76. Let tgate=15ns, calculate the worst case delay for a 32-bit adder. CircuitDelay Ripple Carry (2n+1)tgate65*15ns=975ns Fully Parallel 2*tgate2*15ns=30ns Carry Look Ahead 4*tgate4*15ns=60ns

77. Quiz 4-17

78. Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=0, what is S in ADDER module in hex and decimal?

79. Given the 4-bit add/sub module shown below, let A=$D, B=$F,, what is S? $D+$F=$C -3+(-1)=-4

80. Quiz 4-18

81. Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=1, what is S in hex and decimal?

82. Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=1, what is S? $D-$F=$E -3-(-1)=-2

83. Quiz 4-19

84. Overflow/Underflow Detection Recall That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

85. Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D+$4 2. $6 +$4 3. $7 + $A 4. $F + $F 5. $8 + $F

86. Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D+$4 = $1 (OK) 2. $6 +$4 = $A (O) 3. $7 + $A = $1 (OK) 4. $F + $F = $E (OK) 5. $8 + $F = $7 (U)

87. Quiz 4-20

88. Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D-$7 2. $6 -$4 3. $7 - $A 4. $F - $F 5. $8 - $1

89. Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer. 1. $D-$7=$6 (U) 2. $6 -$4 = $2 (OK) 3. $7 - $A = $D (O) 4. $F - $F = $0 (OK) 5. $8 - $1 =$7 (U)

90. Quiz 4-21

91. Develop the truth table for a 2 bit signed comparator? Your truth table should have four inputs b1 b0 a1 a0 and three outputs F1= (A<B) F2 = (A > B) F3 = (A = B) Assume 2-bit signed (i.e. 2’s comp) values Hint: convert to decimal and compare

92. Solution b1b0a1a0A<BA>BA=B 0000001 0001010 0010100 0011100 0100100 0101001 0110100 0111100

93. Solution b1b0a1a0A<BA>BA=B 1000010 1001010 1010001 1011010 1100010 1101010 1110100 1111001

94. Quiz 4-22

95. Let A=$C and B=$7 and S[1..0]=00, what is F in hex? F[3..0]

96. Let A=$C and B=$7 and S[1..0]=00, what is F? F[3..0] AND Operation F=$04

97. Quiz 4-23

98. Let A=$C and B=$7 and S[1..0]=10, what is F in hex? F[3..0]

99. Let A=$C and B=$7 and S[1..0]=10, what is F? F[3..0] NOT A Operation F=$03

100. Quiz 4-24

101. Let A=$C and B=$7 and S[1..0]=11, what is F hex? F[3..0]

102. Let A=$C and B=$7 and S[1..0]=10, what is F? F[3..0] XOR Operation F=$0B

103. Quiz 4-25

104. Let A=$3 and B=$4, S[1..0]=00, What is F in hex? B A S

105. B A S F=A+B F=$07 0 0

106. Quiz 4-26

107. Let A=$3 and B=$4, S[1..0]=10, What is F in hex? B A S

108. B A S F=A+1 F=$04 0 0